Texas Instruments Corporation

Nathan Weyer Wright

Charles R Engle

Noel T Gregorio

Richard J Karr

Ronnie R Schkade

James Michael Jarboe, Jr

Nicholas Henry Schutt

Van Ho

A clip for coupling a first board and second board, the first board having plurality of first post coupled thereto, the second board having a plurality of second posts coupled thereto, each second post being a cylinder for receiving a first post, the first and second boards having a predetermined relative position when the second posts fully engage the first posts, each second post having an aperture in a side exposing the interior of the cylinder, each first post having a tapered end and a notch around the posts. The clip includes a base member, the base member being coupled to the second board, a top member, the top member having an aperture therein, and a side member connecting the top member and the base member, the side member fabricated so that an edge of the aperture is forced through the aperture into the interior of the second post, edge being forced into the notch when the first and the second posts are engaged and the first and second boards are in the predetermined relationship.

Apparatus and method for a clip device for coupling a heat sink plate system with a burn-in board system

In a burn-in test configuration wherein a chip board having a plurality of semiconductor chips engages a heat sink board having a plurality of heat sinks. When the boards are operationally engaged, each semiconductor chip has a heat sink spring-loaded against the semiconductor chip. Posts coupled to one board engage posts located on the other board. The engagement of the posts orients and secures the relative positions of the two boards. A clip is provided that secures the relative position of the two boards when the two sets of posts are engaged. To uncouple the two boards, a pressure on the side of the clip permits the two boards to separate.

The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip. According to one aspect, the disclosed method and apparatus identifies certain rows and columns within each of the embedded memory arrays that need to be disabled and also identifies certain redundant rows and columns in the embedded memory array to be activated. According to another aspect, the disclosed method and apparatus generates a map indicating where each of the memory failures occurs in each embedded memory array. If the testing process determines that the embedded memory array cannot be repaired, then a signal is provided directly to an external testing device indicating that the embedded memory array is non-repairable. Similarly, if the testing process determines that the failures in the embedded memory array can be repaired, then a signal is provided directly to an external testing apparatus indicating that the embedded memory array is repairable. Lastly, if no failures are found in an embedded memory array, then a signal is provided to an external testing apparatus indicating that the embedded memory array contains no failures. Based upon these status signals, the external testing device can determine which set of data (i.e., repair data and/or failure map data) to off-load from each embedded memory array and which sets of data to disregard, thereby reducing the memory test time for a device. Another aspect of the disclosed method and apparatus is a data flow control unit that controls the flow of input and output data to each of the embedded memory arrays. This device broadcasts the test program to each of the embedded memory arrays at the same time thereby enabling the simultaneous testing of multiple embedded memory arrays. Yet another aspect of the disclosed method and apparatus is a shorthand notation for indicating where memory failures occur within an embedded memory array.

Method and apparatus for testing embedded memory on devices with multiple processor cores

An apparatus for transferring heat from semiconductor devices during a burn-in operation is disclosed. The apparatus includes a substantially planar base board through which a plurality of openings are extended. Heat sinks coordinated with the openings are connected to biasing members and come in contact with the semiconductor devices during the burn-in operation for transferring heat from the devices.

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Missouri City, TX, United States of America

Nathan Weyer Wright