Texas Instruments Corporation

Nathan Richard Schemm

Lei Ding

Rahmi Hezar

Aritra Banerjee

Baher S Haroun

Rajarshi Mukhopadhyay

Cetin Kaya

Joonhoi Hur

Rajdeep Bondade

Serkan Dusmez

Yong Xie

Salil Chellappan

Xiaonan Wang

A short circuit detection circuit includes a current terminal, a sense resistor, an amplifier, and a resistor-capacitor ladder. The sense resistor is coupled to the current terminal, and is configured to develop a sense voltage proportional to a current through the current terminal. The amplifier is coupled to the sense resistor, and is configured to generate a scaled current proportional to the sense voltage. The resistor-capacitor ladder is coupled to the amplifier, and is configured to generate a measurement voltage that represents a surface temperature rise due to the current through the current terminal.

Transistor short circuit protection

Methods, apparatus, systems and articles of manufacture to trim temperature sensors are disclosed. An example method includes: sampling a first value indicative of a temperature of a first die of a multi-chip module (MCM) with a first temperature sensor, the first die including a first transistor having a channel including a first material; and calibrating a second temperature sensor configured to sample a second value indicative of a temperature of a second die including a second transistor have a second channel including a second material, the calibrating based on the first value.

Methods and apparatus to trim temperature sensors

Methods, systems, and apparatus to facilitate a fault triggered diode emulation mode of a transistor. An example apparatus includes a driver to output a control signal to a gate terminal of a transistor of a power converter; and a diode emulation control circuit to, in response to determining a fault corresponding to the transistor, enable the transistor when current flows in a direction from a source terminal of the transistor to a drain terminal of the transistor.

Methods, apparatus, and systems to facilitate a fault triggered diode emulation mode of a transistor

A fault detection circuit includes a short circuit comparison circuit which has a first input connected to the source of the second NFET, a second input, and an output. The circuit includes an over-current comparison circuit which has a first input connected to the source of the second NFET, a second input, and an output. The circuit includes a voltage divider circuit which has a first terminal connected to first input of the short circuit comparison circuit, a second terminal connected to the first input of the over-current comparison circuit, and a third terminal connected to a ground terminal. The circuit includes a delay circuit which has an input connected to the output of the over-current comparison circuit and has an output.

Fault detection circuits and methods for drivers

Methods, apparatus, systems and articles of manufacture are described to parallelize transistors. An example apparatus includes a first transistor on a first die and a second transistor on a second die. The example apparatus includes a parallel feedback terminal coupled to the first die and the second die and a current sensor including a first contact and a second contact. The example apparatus includes a resistor coupled to the current sensor and at least one of the switched terminal or a ground terminal. The example apparatus includes an active drive controller including a first input coupled to the resistor, a second input coupled to the parallel feedback terminal, and an output coupled to the parallel feedback terminal. The example apparatus includes an edge delay controller adapted to be coupled to a gate driver and an error amplifier, and a control contact adapted to be coupled to the gate driver.

Apparatus and methods to parallelize transistors

A first branch group circuit includes a first branch circuit receiving a first RF input signal and first control information; and a second branch circuit receiving the first input signal and second control information. Each of the first and second branch circuits includes a power amplifier. The second control information enables the second branch circuit to be switched on or off while the first branch circuit remains on. A second branch group circuit includes: a third branch circuit receiving a second RF input signal and third control information; and a fourth branch circuit receiving the second input signal and fourth control information. Each of the third and fourth branch circuits includes a power amplifier. The fourth control information enables the fourth branch circuit to be switched on or off while the third branch circuit remains on. A combiner combines output signals of the power amplifiers to produce an output signal.

Multi-branch outphasing system and method

In described examples, bootstrap diode circuits include a first diode having a first diode input coupled to a voltage supply and a first diode output. Described bootstrap diode circuits additionally include a second diode having a second diode input coupled to the first diode output and a second diode output and a plurality of zener diodes coupled in series. The series-coupled zener diodes are further coupled in parallel with the second diode.

Bootstrap diode circuits

A circuit includes an amplifier to amplify an input signal and generate an output signal. The circuit also includes a tuning network to tune frequency response of the amplifier. The tuning network includes at least one tunable capacitor, which includes at least one micro-electro mechanical system (MEMS) capacitor. The amplifier could include a first die, the at least one MEMS capacitor could include a second die, and the first die and the second die could be integrated in a single package. The at least one MEMS capacitor could include a MEMS superstructure over a control structure, which is to control the MEMS superstructure and tune the capacitance of the at least one MEMS capacitor.

Tunable power amplifier with wide frequency range

An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.

Ring amplitude measurement and mitigation

A level shifter includes a signal generator that generates differential signals on a first output and a second output. A first capacitor is coupled between the first output and a first node and a second capacitor is coupled between the second output and a second node. A third capacitor is coupled between the first node and a first voltage potential, wherein the capacitance of the third capacitor is variable. A fourth capacitor is coupled between the second node and the first voltage potential, wherein the capacitance of the fourth capacitor is variable.

Level shifter and method of calibration

An apparatus to monitor and control a switching rate in a switch includes a differentiator circuit including a capacitor and a configurable resistor. The differentiator circuit further includes an input terminal of the capacitors configured to receive a first voltage from a switch and a differentiator node configured to receive a differentiated voltage based on the first voltage. The apparatus includes a peak detector circuit coupled to the differentiator node and configured to detect a peak value of the differentiated voltage. The apparatus further includes a driver circuit coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak value of the differentiated voltage.

Switching rate monitoring and control

An outphasing amplifier includes a first class-E power amplifier having an output coupled to a first conductor and an input receiving a first RF drive signal. A first reactive element is coupled between the first conductor and a second conductor. A second reactive element is coupled between the second conductor and a third conductor. A second class-E power amplifier includes an output coupled to a fourth conductor and an input coupled to a second RF drive signal, a third reactive element coupled between the second and fourth conductors. Outputs of the first and second power amplifiers are combined by the first, second and third reactive elements to produce an output current in a load. An efficiency enhancement circuit is coupled between the first and fourth conductors to improve power efficiency at back-off power levels. Power enhancement circuits are coupled to the first and fourth conductors, respectively.

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Rowlett, TX, United States of America

Nathan Richard Schemm