Agere Systems Guardian Corp.

Lucent Technologies Inc.

Nathan R Belk

Turgut Sefket Aytur

Michel Ranjit Frei

David John Bishop

Ya-Hong Xie

Bradley Paul Barber

Peter Ledel Gammel

William Thomas Cochran

Shahriar Moinian

Mark Richard Pinto

Kwok K Ng

David Clayton Goldthorp

A direct conversion transmitter comprising two local oscillators, an in-phase and quadrature modulating signal and in-phase and quadrature modulators, adds a leakage detector and corrective algorithm with one or more digital to analog converters to generate a corrective signal. The corrective signal corrects for, minimizes, and suppresses local oscillator carrier leakage into the transmitted signal. In accordance with the invention, direct up transmitter carrier leakage is automatically measured at regular intervals during the transmit cycle. A DC correction, or a correction waveform as a function of time, is input to both the 'in-phase' and 'quadrature' modulators at the baseband input. The two correction signals are tuned according to a minimization algorithm to achieve the lowest possible carrier component in the spectral output of the transmitter at its ambient operating conditions and present power output level. As the ambient conditions, such as temperature, and transmitter power level changes, the two correcting input DC currents, or correction waveforms, are further tuned towards the optimal values for that operating condition. Optimization is accomplished by an adaptive feedback technique employed to achieve maximum carrier suppression.

Method and apparatus for suppressing local oscillator leakage in a wireless transmitter

Baseband receiver circuitry is dynamically biased in a communication system receiver by generating gain control information, and controlling an adjustable bias of at least a portion of the baseband circuitry based at least in part on the gain control information. The baseband receiver circuitry comprises at least one amplifier having an adjustable bias associated therewith, with the adjustable bias of the amplifier being controllable utilizing a bias control signal. For example, the amplifier may be an operational amplifier having a gain stage and an output buffer stage, with the bias control signal being applied to the output buffer stage to control an adjustable bias current thereof. More specifically, the bias control signal may be used to control an amount of current provided by at least one of a plurality of current sources associated with the output buffer stage of the amplifier, for example, by controlling a switch which enables or disables one or more of the current sources. Advantageously, the dynamic bias control can substantially reduce power consumption in the receiver. The techniques of the invention can also be applied to other types of devices which utilize gain control.

Method and apparatus for dynamic biasing of baseband circuitry in a communication system receiver

A radio frequency (RF) module for use in a communication device of a communication system includes integrated RF circuitry comprising at least one of a transmitter and a receiver, and an antenna element having at least one portion thereof arranged substantially adjacent to and operatively coupled to the integrated RF circuitry. For example, the antenna element may include at least first and second portions having opposing edges arranged immediately adjacent respective first and second sides of the integrated RF circuitry. A plurality of the modules can be used to implement a transceiver in a communication system base station or other communication device.

Communication system transmitter or receiver module having integrated radio frequency circuitry directly coupled to antenna element

An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

Inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit

Metalization structures are modeled by employing a basis function decomposition process for modeling the charge and/or current distributions and the interactions of those distributions on metalization structures arising from voltages and currents flowing in the metalization structures. Then, the charge and/or current distributions and their interactions are employed to obtain the electrical characteristics of a metalization structure. In one embodiment of the invention, representative sub units of the metalization structure are selected, the charge and current distributions are determined in those representative sub units, the self and mutual interactions are determined of those sub units and, then, those self and mutual interactions are used as an initial solution to describe all interactions between similar metalization sub units in the overall system of metals. These interactions are then employed to determine the impedance and admittance of each of the sub units. The impedances and admittances of the sub units are combined to obtain the overall metalization structure to be fabricated. Then, the electrical characteristics of the overall metal structure are determined. In another embodiment of the invention, the metal structure is decomposed into sub units. Repeated or representative ones of the sub units are determined and, then, decomposed into smaller sub unit elements. Sub unit impedances and admittances are determined for the sub units by using the current and/or charge distributions and their self and mutual interactions for the sub unit elements. Then, the impedances and admittances for the sub units are combined to obtain the overall metalization structure to be fabricated. Finally, the electrical characteristics are generated of the overall metalization structure.

Method and apparatus for modeling electromagnetic interactions in electrical circuit metalizations to simulate their electrical characteristics

Metalization structures are modeled by employing automatic substrate grounding and shielding generation in conjunction with a design and simulation process for modeling the charge distributions and the interactions of these charge distributions on metalization structures arising from voltages and currents flowing in metalization structures. By generating and, then, employing a grounding structure that is optimized to strongly screen the metalization structure being designed and simulated, the requirement is eliminated for the accurate incorporation of the strongly dependent long range metalization sub unit to sub unit charge distribution coupling from the charge distribution determination process. In one embodiment of the invention, representative metalization sub units are selected, such as straight sections of infinitesimal length, right angle bends and intersections. Charge distributions are determined in those representative sub units based on the assumption that the integrated circuit substrate strongly suppresses any long range circuit interactions or frequency dependent effects. Then, based on the above assumption, self and mutual interactions are determined of the metalization sub units. Further, based on determined characteristics of those sub units, substrate grounding structures are determined and constructed that ensure the validity of the simulation assumption that the substrate grounding is adequate to strongly suppress any long range circuit interactions and/or frequency dependent effects. The determined self and mutual interactions can then be used as initial solutions to describe all interactions between similar metalization sub units in the overall physical metalization structure to be fabricated.

A so-called multipole decomposition is employed for modeling the charge and current distributions and the interactions of those distributions in metalization sub units arising from electrical signals in those metalization sub units. Specifically, a variable interaction range meshing, i.e., multipole, decomposition process is advantageously employed to model the charge and current distributions of metalization sub units. These distributions are then employed to obtain electrical characteristics of an overall physical metalization structure to be fabricated. In an embodiment of this invention, representative sections of metalization sub units are selected such as straight sections of infinitesimal length, right angle bends and intersections, and solved for the local short range charge and current interactions that determine their local distributions in those sub units. Then, components of the charge and current distributions are selected and separated based on the nature of their interactions with other circuit metalization sub units and the rate at which they can vary in the metalization structure. Only those interactions are retained that can significantly impact the overall metalization structure characteristics and only evaluate those interactions with other metalization sub units during intervals during which those interaction components are capable of changing.

Electrodynamically determined electric field and/or current distributions are employed in conjunction with statically determined electric field distributions localized to metalization structures on a conductive substrate to model metal structures to be fabricated on a substrate. Specifically, the static electric field distributions are subtracted from the electrodynamic field distributions and the results are used to determine the electrodynamic component of self and mutual interactions between metalization structures to be fabricated on the conductive substrate. Then, statically determined current interactions of the metalization structures to be fabricated are determined and superimposed on the electrodynamic interactions. The results of the superimposition are used to generate the overall integrated circuit metal structure to be fabricated on the conductive substrate. In a specific embodiment of the invention, a static determination of electric field distributions caused by a time invariant point current source is obtained in the absence of the substrate and subtracted from the electrodynamically obtained electric field distributions from the interaction of a vector potential caused by a time variant point current in the presence of the substrate. The resulting difference values that are valid for all metalization structures fabricated on this type of substrate are stored in a look-up table. Then, when a simulation of the interactions, for example, of an inductor or other system of metals, on a conductive substrate is made the weakly spatially dependent electrodynamic component of the substrate interactions from the look-up table are superimposed on a very efficiently determined static solution for the inductor or other system of metals being simulated. The results of the superimposition are used to generate the overall integrated circuit metal structure on the conductive substrate.

Method and apparatus for quasi full-wave modeling of interactions in circuits

An article comprising a micro-machined, passively self-assembling inductor is disclosed. The inductor is fabricated using MEMS technology and advantageously utilizes materials compatible with CMOS such that inductor is monolithically integrable with a CMOS chip. The inductor includes passive self-assembly means by which the inductor loop is moved away from an underlying substrate, typically silicon, in the final steps of inductor assembly. Such passive self-assembly does not require separate actuation or monitoring steps.

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Scotch Plains, NJ, United States of America

Nathan R Belk