Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies Wireless IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Nathan Perkins

Jonathan Kwadwo Abrokwah

Timothy Arthur Valade

Albert William Wang

Thomas Edward Dungan

John H Stanback

Hans G Rohdin

Robert G Long

Ricky Snyder

Scott A Rumery

Philbert Marsh

An apparatus includes a multilayer package substrate having a plurality of layers. The apparatus also includes a first heat sink disposed over the package substrate. The first heat sink is configured to connect to a semiconductor device and to provide an electrical ground for the semiconductor device. The apparatus includes a second heat sink disposed in the package substrate. The first heat sink overlaps substantially all of the first electrically conductive layer and no dielectric material exists in the multilayer package substrate in a region of contact of the first heat sink and the first electrically conductive layer.

Apparatus and semiconductor structure including a multilayer package substrate

A thermally conductive and electrically insulating layer is provided over a semiconductor structure.

Semiconductor structure including a thermally conductive, electrically insulating layer

A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes a thermally conductive core disposed in the recess, and a package substrate including a heat sink. The heat sink is in thermal contact with the thermally conductive core.

Semiconductor structure having thermal backside core

A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.

Passivation for group III-V semiconductor devices having a plated metal layer over an interlayer dielectric layer

A pseudomorphic high electron mobility transistor (PHEMT) comprises a substrate comprising a Group III-V semiconductor material, a buffer layer disposed over the substrate, wherein the buffer layer comprises microprecipitates of a Group V semiconductor element and is doped with an N-type dopant, and a channel layer disposed over the buffer layer.

Pseudomorphic high electron mobility transistor comprising doped low temperature buffer layer

A method of fabricating a semiconductor device is disclosed. The method comprises patterning a photoresist over a compound semiconductor substrate; reducing a width of the photoresist; forming a hardmask over the substrate and not over the photoresist; removing the photoresist; etching to form and opening down to the substrate; forming a gate in the opening; and removing the hardmask except beneath the gate.

Method for producing a transistor gate with sub-photolithographic dimensions

A method of fabricating a semiconductor device, the method comprises forming a mask layer over a compound semiconductor substrate; and patterning a photoresist over the mask layer. The method comprises etching a portion of the mask layer beneath the photoresist; forming a hardmask over the substrate and not over the mask layer; removing the mask layer; etching to form and opening down to the substrate; and forming a gate in the opening.

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Windsor, CO, United States of America

Nathan Perkins