Tokyo Electron Limited

Nathan Ip

Carlos A Fonseca

Joel Estrella

Anton J deVillers

Joshua Hooge

Norifumi Kohama

Satoshi Itoh

Megan Wooley

Soudai Emori

Nima Nejadsadeghi

A wafer bonding apparatus including: a first chuck in a processing chamber, the first chuck being configured to hold a first wafer, the first chuck including: a chuck body, and a tunable stiffness layer including a plurality of actuators, the plurality of actuators including a tunable stiffness material, the tunable stiffness layer being disposed below the chuck body; a controller configured to send control signals to one or more of the plurality of actuators; and a vacuum line on the chuck body configured to apply a vacuum pressure from a vacuum pump to the first wafer; and a second chuck in the processing chamber, the second chuck being configured to hold a second wafer to be bonded with the first wafer; and where a stiffness of the plurality of actuators is configured to change based on the control signals from the controller.

Wafer chuck with tunable stiffness material

Sensitivity calculations are provided of a process model through the rate of change of a model fingerprint with respect to process variables and defects. A fingerprint sensitivity table is generated, where process variables are associated with a set of fingerprint sensitivities. The fingerprint of incoming substrates is monitored through a production process by applying the same fingerprint method that is used in the process model. Calculations are made of the difference between the incoming substrate fingerprint and the process model predicted fingerprint. This difference fingerprint is compared against the table of fingerprint sensitivities to find the process variable most likely to be responsible for the difference. Spatial relationships between process variables and actual measurements on the substrate may be obtained. Correlation through fingerprint sensitivity improves the ability to pinpoint faulty process tools. The difference fingerprint may also identify the formation of defects on a substrate.

Method and process using fingerprint based semiconductor manufacturing process fault detection

Various embodiments of wafer bonding apparatuses and methods are described herein for reducing distortion in a post-bonded wafer pair. More specifically, the present disclosure provides embodiments of wafer bonding apparatuses and methods to reduce post-bond wafer distortion that occurs primarily within the center and/or the edge of the post-bonded wafer pair. In the present disclosure, post-bonded wafer distortion is reduced by correcting for variations in the pre-bond wafer shapes. Variations in pre-bond wafer shape are corrected, or compensated for, by making hardware modifications to the wafer chuck. Such modifications may include, but are not limited to, modifications to the surface height and/or the temperature of the wafer chuck. Although hardware modifications are disclosed herein for reducing post-bond wafer distortion near the center and/or the edge of the post-bonded wafer pair, similar modifications can be made to reduce post-bond wafer distortion within other areas or zones of the post-bonded wafer pair.

Wafer bonding apparatus and methods to reduce post-bond wafer distortion

A plasma processing method that is executed by a plasma processing apparatus including a processing container containing a target substrate, a plurality of plasma sources, and a gas supply apparatus for supplying gas includes: supplying the gas from the gas supply apparatus into the processing container; individually controlling intensity of power introduced from each of the plurality of plasma sources into the processing container; and generating plasma of the gas by the intensity of the power introduced from each of the plurality of plasma sources and depositing a desired film on a second surface of the target substrate that is an opposite surface of a first surface of the target substrate so as to apply desired film stress to a film on the first surface.

Plasma processing method and plasma processing apparatus

Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Enhancement of yield of functional microelectronic devices

A method includes having a first wafer bonding recipe and a model of a wafer bonding process, the model comprising an input indicative of a physical parameter of a first wafer to be bonded to a second wafer and configured to output a wafer bonding recipe based on the physical parameter of the first wafer; obtaining measurements of the first wafer to obtain the physical parameter of the first wafer; generating, by the model, the first wafer bonding recipe based on the physical parameter of the first wafer; and bonding the first wafer to the second wafer in accordance with the first wafer bonding recipe to produce a first post-bond wafer.

Apparatus and methods for wafer to wafer bonding

In one embodiment, a method includes obtaining wafer measurements of a characteristic of a semiconductor wafer at each of a plurality of process steps during a semiconductor wafer fabrication process, where each of the wafer measurements is associated with a spatial location on the semiconductor wafer from which the measurement is obtained. The method may further include creating a process step fingerprint from the obtained wafer measurements for each process step. The method may further include correlating the process step fingerprint of one of the plurality of process steps to the process step fingerprint of another one of the plurality of process steps to produce a transfer function.

Systems and methods for manufacturing microelectronic devices

Disclosed herein is a technology related to the amelioration (e.g., correction) of global wafer distortion based on a determination of localized distortions of a semiconductor wafer. Herein, a distortion is either an out-of-plane distortion (OPD) or in-plane distortion (IPD). The reference plane for this distortion is based on the plane shared by the surface of a presumptively flat semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

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Austin, TX, United States of America

Nathan Ip