Sandisk Technologies Inc.

Intel Corporation

Nathan Franklin

Ward M Parkinson

Michael Grobis

James E O'Toole

Michael Nicolas Albert Tran

Kiran Pangal

Thomas Michael Trent

Kyu S Min

Qing Ma

Raj K Ramanujan

Valluri Ramana Rao

Pranav Kalavade

Martin Aureliano Hassner

Li-Peng Wang

Christopher John Petti

Krishna Kumar Parat

Mark Alan Helm

Jeffrey Scott Lille

Sandeep K Guliani

Mase J Taub

Martin Lueker-Boden

Quan Anh Tran

Prashant S Damle

Daniel Chu

Matthew Goldman

Donald E Adams

Robert N Stark

Hans Jurgen Richter

James W Reiner

Lunkai Zhang

Gayathri Rao Subbu

Yevgeny Anoikin

Byong Man Kim

Hu Chaohong

A bypass buffer stores codewords that have been identified as worn out codewords due to stuck-at-failure bit errors and/or other endurance failures. A controller of a data storage device monitors the number of worn out bits of a codeword stored by a memory device of the data storage device. If the number of worn out bits of the codeword exceeds a threshold number of worn out bits, data associated with the codeword is corrected and stored in the bypass buffer. The memory address associated with the codeword is also stored in the bypass buffer and associated with the corrected codeword.

Bypass buffer for worn out codewords

A spin-orbit-torque (SOT) memory cell includes a first electrode embedded in dielectric material layers overlying a substrate; a magnetic-tunnel-junction-containing (MTJ-containing) pillar structure contacting a top surface of the first electrode and including a pinned layer and a free layer that overlies the pinned layer; a spin current metal line including a center portion that contacts the MTJ-containing pillar structure; and a selector element electrically connected to a first end of the spin current metal line.

SOT MRAM including MTJ and selector located on opposite sides of SOT layer and method of making the same

Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.

Cross-point array refresh scheme

Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

Concurrent multi-bit self-referenced read of programmable resistance memory cells in cross-point array

Concurrent write to programmable resistance memory cells in cross-point array

Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector.

Cross-point array IHOLD read margin improvement

Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.

Mixed current-forced read scheme for MRAM array with selector

Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).

Programmable ECC for MRAM mixed-read scheme

A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.

Signal amplification in MRAM during reading, including a pair of complementary transistors connected to an array line

Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

Forced current access with voltage clamping in cross-point array

Concurrent multi-bit access in cross-point array

Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.

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San Mateo, CA, United States of America

Nathan Franklin