International Business Machines Corporation

Nathan Fontenot

Michael Thomas Strosaker

Joel Howard Schopp

Jacob Lorien Moilanen

George Conerly Wilson

Ryan Patrick Grimm

Jeffrey David George

Christopher J Arges

Mark Wayne VanderWiele

Fionnuala G Gunter

Manish Ahuja

Robert Cory Jennings, Jr

Monty Christoph Poppe

Michael T Strosker

Christy L Norman

Systems, methods, and computer-readable media are described for selecting, at build time, a respective compiler and/or a respective set of compiler options for each section of code to be compiled such that the compiler/compiler options selected for each code section are optimized for that code section with respect to one or more metrics. Abstract syntax tree (AST) analysis and semantic analysis may be performed at build time for each section of code to identify the compiler/compiler options that produce compiled object code for that code section that maximizes or minimizes a desired metric. The metric according to which compiler/compiler option optimization is performed may be any suitable metric including, without limitation, performance, binary size, security, reliability, scalability, and so forth.

Build-time code section-specific compiler selection

A source code search comprises a two-pass search. The first pass comprises a topological measure of similarity. The second pass comprises a semantic measure of similarity. The query source code is a user-selected portion of source code. The results may be ranked and output to an I/O device.

Source code search engine

Embodiments relate to a virtualized storage environment with one or more virtual machines operating on a host and sharing host resources. Each virtual machine has a virtual disk in communication with a persistent storage device. The virtual machine(s) may be misaligned with the persistent storage device so that a virtual block address does not correspond with a persistent storage block address. A relationship between the virtual disk(s) and the persistent storage device is established, and more specifically, an alignment delta between the devices is established. The delta is employed to translate the virtual address to the persistent address so that the virtual and persistent storage blocks are aligned to satisfy a read or write operation.

Virtual disk alignment access

According to one embodiment of the present disclosure, an approach is provided in which a processor selects a page of data that is compressed by a first compression algorithm and stored in a memory block. The processor identifies a utilization amount of the compressed page of data and determines whether the utilization amount meets a utilization threshold. When the utilization amount fails to meet the utilization threshold, the processor uses a second compression algorithm to recompresses the page of data.

Multi-level memory compression

A method, system, and computer program product for managing system resources within a data processing system. A resource management moderator (RMM) utility assigns a priority to each application within a group of management applications, facilitated by a RMM protocol. When a request for control of a particular resource is received, the RMM utility compares the priority of the requesting application with the priority of the controlling application. Control of the resource is ultimately given to the management application with the greater priority. If the resource is not under control of an application, control of the resource may be automatically granted to the requester. Additionally, the RMM utility provides support for legacy applications via a 'manager of managers' application. The RMM utility registers the 'manager of managers' application with the protocol and enables interactions (to reconfigure and enable legacy applications) between the &#x201c;manager of managers&#x201d; application and legacy applications.

System resource management moderator protocol

A method for resetting of memory locks in a transactional memory system. The method includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The method further includes determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.

Resetting memory locks in a transactional memory system

Source code for a function of a computer program is compiled by compilers to generate executable code variants for the function according to different optimization approaches. Each executable code variant is executable on a same processor architecture. A binary file for the computer program is constructed that includes each executable code variant. At runtime of the binary file, one of the executable code variants is selected for the function. The selected executable code variant is used during execution of the computer program, until execution is halted.

Binary file for computer program having multiple executable code variants for a function that are executable on a same processor architecture

A method, system, and computer program product for the prioritization of code execution. The method includes accessing a thread in a context containing a set of code instances stored in memory; identifying sections of the set of code instances that correspond to deferrable code tasks; executing the thread in the context; determining that the thread is idle; and executing at least one of the deferrable code tasks. The deferrable code task is executed within the context and in response to determining that the thread is idle.

Post-return asynchronous code execution

A system and computer program product for resetting of memory locks in a transactional memory system. The system includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The system further includes the processor determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.

Each time a currently scheduled virtual machine (VM) accesses a hardware resource over a bus for the hardware resource via the currently scheduled VM running on a processor, a hardware component adjusts a bandwidth counter associated with usage of the bus for the hardware resource, without involvement of the currently scheduled VM or a hypervisor managing the currently scheduled VM. Responsive to the bandwidth counter reaching a threshold value, the hardware component issues an interrupt for handling by the hypervisor to maintain bandwidth quality-of-service (QoS) of bus bandwidth related to the hardware resource. Upon expiration of a regular time interval prior to the bandwidth counter reaching the threshold value, the hardware component resets the bandwidth counter to a predetermined value associated with the currently scheduled VM, without involvement of the currently scheduled VM or the hypervisor; the hardware component does not issue an interrupt. The hardware resource can be memory.

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Georgetown, TX, United States of America

Nathan Fontenot