Hewlett-packard Development Company, L.p.

Nathan Dirk Zelle

Anand V Kamannavar

Sahir Shiraz Hoda

Gary Belgrave Gostin

Harry David Foster

Bradley Forrest Bass

Timothy Pertuit

Brad F Bass

Robert John Porter

David John Lacey

Erich Matthew Gens

Exemplary techniques for model curation are described. In a described embodiment, a method comprises generating a manifest of a plurality of files corresponding to a design model; utilizing a revision control system to determine whether the generated manifest has changed relative to a previous version of the manifest; and if the generated manifest has changed, obtaining copies of the plurality of files to validate stability of the design model and curating the design model.

Model curation for integrated circuit designs

A database system including an encoder module and a revision control archive module is disclosed. The encoder module receives signals representing a database access request, generates database access commands, and executes the database access command against a revision control archive module if the database access command causes a change to a data record in the database.

Database modification history

Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification command to verify a portion of a hardware design of a device under test. The error verification object is compiled in accordance with data provided by an error scripting module. The error scripting module has access to hardware-specific data corresponding to the hardware design of the device under test. The compiled object is sent to the device under test and a response to the compiled object is received from the device under test. The received response from the device under test is parsed in accordance with data provided by the error scripting module.

Hardware verification scripting

In one embodiment, the present invention is directed to a method for inserting errors into data to facilitate validation of an error detection algorithm. The method comprises: receiving a data corruption command for a plurality of bits; determining, from the data corruption command, a plurality of bit fields within the plurality of bits for data corruption; determining a minimum and maximum number of errors for each of the plurality of bit fields; determining a total number of errors to be inserted; inserting the minimum number of errors into each of the plurality of bit fields at random locations; and randomly inserting additional errors into the plurality of bit fields subject to the maximum number of errors until the total number of errors are inserted.

Systems and methods for scripting data errors to facilitate verification of error detection or correction code functionality

One embodiment of a computer system has processors, having address spaces the processors can address directly. Each address space is directly linked to at least one other address space by memory within more than its own address space. The total size of the address spaces within the system linked together either directly or through directly linked address spaces is greater than the address space any resource within the system can address directly.

Communication in partitioned computer systems

Exemplary techniques for utilizing architecture specific code are described. In a described embodiment, a method comprises storing architecture specific design verification code in a plurality of architecture specific code libraries. Each of the architecture specific code libraries corresponds to a select generation of architecture. The method further verifies a design of the select architecture by utilizing a corresponding architecture specific code library from the plurality of architecture specific code libraries and a non-architecture specific code library. The non-architecture specific code library corresponds to at least two different generations of the architecture.

Architecture specific code

A system and method for automatic verification of a test plan for a semiconductor device. The device is specified by a hardware description language (HDL) model or a formal description language model derived from the HDL model. A test plan tool and database are provided to capture test item definitions and identifications and a monitor generator is provided to generate monitors for detecting functional coverage during verification. An evaluator is provided to compare verification-events with test-plan items, to determine test item completeness and to update the test plan database.

Growing community of inventors

Dallas, TX, United States of America

Nathan Dirk Zelle