International Business Machines Corporation

Intel Corporation

Nathan D Jack

Souvick Mitra

James Paul Di Sarro

Robert J Gauthier, Jr

Ayan Kar

Kalyan C Kolluru

Nicholas A Thomson

Tahir Ghani

JunJun Li

Biswajeet Guha

Oleg Golonzka

William Hsu

Kinyip Phoa

Shunhua Thomas Chang

Chung-Hsun Lin

Benjamin Orr

Rishabh Mehandru

Patrick R Morrow

Mark T Bohr

Rui Ma

Jun Jun Li

Robert J Gauthier

Halady Arpit Rao

Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact

Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

Gate-all-around integrated circuit structures having adjacent deep via substrate contacts for sub-fin electrical contact

Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact

Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.

Substrate-less FinFET diode architectures with backside metal contact and subfin regions

Integrated circuit (IC) strata including one or more transistor and one or more semiconductor diode. A transistor may include one or more non-planar semiconductor bodies in which there is a channel region while the diode also includes one or more non-planar semiconductor bodies in which there is a p-type region, an n-type region, or both. One IC stratum may be only hundreds of nanometers in thickness and include both front-side and back-side interconnect levels. The front-side interconnect level is disposed over a front side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the transistor. The back-side interconnect level is disposed over a back side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the semiconductor diode.

Semiconductor diodes employing back-side semiconductor or metal

An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers

A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.

Integrated circuit protection during high-current ESD testing

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Hillsboro, OR, United States of America

Nathan D Jack