Motorola Corporation

Nathan Baron

Judah L Adelman

Avner Goren

Yehuda Volpert

Paul Marino

Eyal Melanmed-Cohen

An integrated circuit chip includes a processor (4) and a memory (10) coupled by data and address buses (PAB, PDB). The memory is switchable between a first, standard, mode of operation in which a memory controller (14) is operative and a second, cache, mode of operation in which a cache controller (12) is operative by a switch (16, 22, 40). A memory area includes a valid bits array (VBA), a bit of which is set when a valid word is stored in a respective memory address of the memory in standard mode. If a valid bit exists corresponding to an address on the address bus, then information loaded into the memory in standard mode can be used by the processor in cache mode. The operating mode of the memory is switched using an operating mode register having a cache enable section, and a cache enable control line coupled to the memory. A reset arrangement is provided for resetting the valid bits array to flush the cache in a single operation. In one preferred embodiment, the cache is an instruction cache and the integrated circuit chip is a digital signal processor (DSP).

Real time cache implemented by on-chip memory having standard and cache

A voltage controlled oscillator (VCO) (2) provides an output signal which has a 50% duty cycle and a frequency which depends on the voltage of a control signal (V) supplied thereto. The VCO (2) comprises first (C.sub.L) and second (C.sub.R) capacitors and first (3) and second (5) circuits. Each of the first and second circuits comprises a current supply arrangement (10, 12, 14, or 18, 20, 22) coupled to a respective one of the capacitors (C.sub.L or C.sub.R) and to receive the control signal (V), and a Schmitt trigger (6 or 16) coupled to the respective current supply arrangement and to the other capacitor, which is not coupled to the respective current supply arrangement. Each current supply arrangement of the first and second circuits alternately charges and discharges the respective capacitor, in dependence on the switching of the respective Schmitt trigger, so that the VCO (2) oscillates between the charging of the first and the charging of the second capacitor. The rate of charging of the first and second capacitors is dependent on the voltage of the control signal (V).

Voltage controlled oscillator having a 50% duty cycle

A lock detection circuit (2) for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal (REFERENCE). The lock detection circuit includes a circuit for generating first (UP) and second (DOWN) pulses, the first and second pulses respectively representing positive and negative differences between a parameter, such as phase, of the PLL signal and a parameter of the reference signal, and a first counter (4) for counting sets of first and second, pulses, each set comprising a first pulse followed by a second pulse, the first counter on counting a predetermined number of sets of pulses providing a first count complete signal. The lock detection circuit further includes a second counter (6) for counting transitions of the reference signal (REFERENCE), and being coupled to the circuit for generating whereby the second counter is reset by the first (UP) or second (DOWN)pulse, the second counter (6) on counting a predetermined number of transitions of the reference signal providing a second count complete signal, and a logic circuit (20) for generating a signal (LOCK) indicating lock has been achieved in response to the receipt of either the first or second count complete signal. Preferably, the lock detection circuit further includes a pulse width detection circuit (30) for detecting the widths of the first and second pulses and in response to detecting the width of either of the first or second pulse is greater than a predetermined value for providing a reset signal which resets the first and second counter.

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Oranit, Israel

Nathan Baron