Unisys Corporation

Nathan A Eckel

Gregory B Wiedenman

Kelvin S Vartti

Gary J Lucas

Joel B Artmann

Mary C Roskowiak

Peter Levinshteyn

Raymond G Ryan

The current invention provides a mechanism for detecting and recovering from glitches on data strobes. In one embodiment, data is captured from an interlace by a receiver using at least one data strobe that is provided by the transmitter along with the data. A write address counter that is clocked by the data strobe is used to count the active edges of the data strobe. A read address counter that is periodically synchronized with the write address counter, but that is clocked by an internal clock of the receiver, is used to count units of data being received from the interface. Periodically, the contents of the read and write counters are compared. If the contents are not the same, a glitch has occurred on the data strobe. The glitch is recoverable if it occurs on, or after, a last strobe edge of a data transfer.

System and method for detecting glitches on a high-speed interface

A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system interface bus. The deferring agent is allowed to look ahead to determine if a continuous stream of defer phase cycles are pending transfer. If pending, the deferring agent will not release control of the bus until the pending defer phase cycles have been depleted. The look ahead feature allows expedited return of higher priority defer data, while minimizing bus dead cycles caused by interleaving defer phase cycles with normal bus traffic.

Method and apparatus for providing overlapping defer phase responses

A method and apparatus is presented allowing multiple data pointers or addresses to be transferred without acknowledgment to Memory Controller () and Memory Controller () of Data Controller (). Data is then transferred in response to the data pointers from BUFFER () and Buffer () and may be stalled during the transfer in favor of a second data transfer. Once the second data transfer finishes, the first data transfer may be completed.

Method and apparatus for stacked address, bus to memory data transfer

Bus address, function and system information in relation to bus requests are maintained in a centralized location (). Parallel access to the centralized data is facilitated through the use of pointers to the centralized location. Bus transaction operations needing access to the centralized data are simultaneously connected to the data through the use of the pointer control (), rather than requiring the data to be sequentially transmitted to the bus transaction operations as required.

Method and apparatus for multiple sequence access to single entry queue

A method and apparatus to facilitate a history trace of system bus activity in a Symmetric Multi-Processor (SMP) environment. A dynamic scan capability is provided to User () via Computer () that allows dynamic configuration of History Control Register (), thus providing a maskable history stack of system bus activity to be obtained from History Memory () for subsequent analysis.

Method and apparatus for recording and monitoring bus activity in a multi-processor environment

A data transfer system uses a data buffer and individual control of each storage location within the data buffer for improved control of data block transfers. The storage locations are assigned deallocate, active, or valid assignment bands to enable transfer control of the data blocks within the system. The deallocated storage locations are returned to an allocation pool for use as a future resource, where the active and valid assignment bands remain unavailable until deallocated. Error checking and depth control prohibit consecutive allocation or deallocation assignments as well as overflow.

Buffered transfer of data blocks between memory and processors independent of the order of allocation of locations in the buffer

Coded requests are received from Memory Port Interfaces (and) and stored into Outgoing Queue (). Coded requests are also received from Transaction Pipeline (), some of which may be linked requests. In response to each linked request stored in Outgoing Queue (), multiple bus requests are generated by Outgoing Queue () and assembled by Assembler () and placed onto Bus Interface ().

Growing community of inventors

Fridley, MN, United States of America

Nathan A Eckel