International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Natesan Venkateswaran

Chandramouli Visweswariah

Vladimir P Zolotov

Jeffrey G Hemmett

Eric A Foreman

Kerim Kalafala

Nathan C Buck

Peter Anton Habitz

Debjit Sinha

John P Dubuque

Brian M Dreibelbis

David James Hathaway

Stephen Gerard Shuma

Gregory M Schaeffer

Xiaoyue X Wang

Michael H Wood

Robert J Allen

Alexander Joel Suess

Jayapreetha Natesan

Tsung-Wei Huang

Jinjun Xiong

Vasant B Rao

James Charles Gregerson

Lansing D Pickup

Richard W Taggart

Douglas Keller

Brian Robert Prasky

Yuk Lung Chan

K Paul Muller

Jerry D Hayes

Susan K Lichtensteiger

Gerald Stanquist

Eric Jason Fluhr

Carlos A Hoyos

Jason Hirst

Nagashyamala R Dhanwada

Adil Bhanji

Amol Anil Joshi

Chanchal Saha

Barry Lee Dorfman

Raquel Norel

Peihua Qi

Lizheng Zhang

Glenn E Holmes

Michael Lapointe

William John Wright

Jennifer E Basile

Adam Benjamin Childers

Chaitanya Ravindra Peddawad

Dileep N Netrabile

Stephen G Shurma

Vladimer Zolotov

Chandramouli Viswewariah

Chunming Lin

Joseph K Morrell

Jose Luis P Correia Neves

Sumant Singh Rana

Susan Shumway

Vladmimir Zolotov

A method, system, and computer program product algorithmically analyzes scoring data from a competitive event where the scoring, determined by a plurality of evaluators, is based on subjective criteria. The method receives, and/or determines a scale factor associated with each evaluator. The method adjusts scores awarded by each evaluator, based on respectively corresponding scale factors, to arrive at normalized scores. The method, thereby minimizes influences of biases associated with the evaluators.

Detecting and removing bias in subjective judging

Methods, systems, and computer program products for placement of objects in a loading space are provided. Aspects include determining item data for a plurality of items, determining space data for a loading space, generating an optimized configuration for placement of the plurality of items in the loading space comprising determining one or more geometric representations for each item in the plurality of items, wherein the one or more geometric representations for each item are coupled together, determining, by an algorithm, a location in the loading space for each item in the plurality of items based on the one or more geometric representations for each item and the space data, and displaying, by a display, the optimized configuration comprising an image of each item of the plurality of items overlaid on corresponding locations in an image of the loading space.

Floor planning and placement of objects in a loading space

An embodiment of the invention may include a method, computer program product and system for operating an electronic display device. An embodiment may include displaying, using a first refresh rate, first content on a first partition of a display area of the electronic display device. An embodiment may include displaying, using a second refresh rate, second content on a second partition of the display area of the electronic display device. The first refresh rate is different from the second refresh rate.

Screen capture prevention

Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.

Partial parameters and projection thereof included within statistical timing analysis

Embodiments of the present invention disclose a method, computer program product, and system for parallel access to an electronic design automation (EDA) application. The computer receives a request to access an electronic design automation (EDA) application from at least two user computing device and authenticates a user associated with each of the requests from the at least two user computing devices to access the EDA application. The computer determines a level of access to be granted to each of the user of the at least two user computing devices and creates a parallel connection to each of the at least user computing device based on the determined level of access granted to each of the users. The computer retrieves data to be transmitted to each of the at least user computing device to be displayed on each of the user computing devices and stores the data in a memory unit.

Parallel access to running electronic design automation (EDA) application

A system and method of performing variable accuracy incremental timing analysis in integrated circuit development includes generating a timing graph for interconnected components. The timing graph represents each pin as a node and each interconnection as an arc. A first node or arc is selected. First-level timing values are obtained for the first node or arc using a first timing model that provides a first level of accuracy. n timing models with corresponding n levels of accuracy are pre-selected. The first-level timing values are copied as second-level timing values and as timing values for every other one of the n levels of accuracy for the first node or arc. A second node or arc downstream from the first node or arc is selected. Second-level timing values for the second node or arc are obtained using a second timing model that provides a second level of accuracy.

Variable accuracy incremental timing analysis

Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

Integrating manufacturing feedback into integrated circuit structure design

The computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Multi-sided variations for creating integrated circuits

Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Creating by a computer an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

A method, system, and computer program product for performing incremental common path pessimism analysis in integrated circuit design includes performing common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism. The method also includes identifying one or more post-CPPR critical paths based on the CPPR analysis, setting flags for critical nodes of the one or more post-CPPR critical paths, performing a design fix to address the one or more post-CPPR critical paths, and applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths. Invalidating and re-performing the CPPR analysis is done only for paths associated with the seed points.

Incremental common path pessimism analysis

Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In accordance with aspects of the present disclosure, a computer-implemented method for statistical static timing analysis of an integrated circuit is provided. The method may comprise identifying a timing parameter that contributes to a delay calculation. The method may further comprise determining, by a processing device, whether the identified timing parameter significantly impacts the delay calculation. The method may also comprise, responsive to determining that the identified timing parameter does not significantly impact the delay calculation, avoiding a sensitivity calculation for the identified timing parameter.

Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit

Growing community of inventors

Hopewell Junction, NY, United States of America

Natesan Venkateswaran