Ati Technologies Ulc

Natan Shtutman

Collis Quinn Carter

David I J Glen

Jonathan Wang

Nicholas J Chorney

Michael Foxcroft

Gabriel Abarca

Stephen Ho

Ngar Sze Nancy Chan

An apparatus includes a clock circuit and a virtual pixel clock circuit. The clock circuit provides a common clock signal. The virtual pixel clock circuit provides a plurality of pixel clock signals in response to the common clock signal. One of the virtual pixel clock signals is at a different clock speed than another of the plurality of virtual pixel clock signals.

Pixel clocking method and apparatus

An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.

Display link clocking method and apparatus

Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.

Methods and systems to reduce display artifacts when changing display clock rate

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Richmond Hill, Canada

Natan Shtutman