Intel Corporation

Other

Nasser A Kurd

Praveen Mosalikanti

Vaughn J Grossnickle

Javed Sabir Barkatullah

Mark L Neidengard

Mohamed A Abdelmoneum

Vivek K De

James W Tschanz

Qi S Wang

Robert J Greiner

Alexander Gendler

Kuan-Yueh Shen

Siva G Narendra

Gerhard Schrom

Keng L Wong

David J O'Brien

Thomas P Thomas

Jed D Griffin

Ian A Young

Muhammad M Khellah

Narayan Srinivasa

Christopher P Mozak

Edward Allyn Burton

Ehud Reshef

Gerald S Pasdast

Mohammad Mamunur Rashid

Ido Ouzieli

Tarek A Ibrahim

Tim Frodsham

Jonathan P Douglas

Dong-Ho Han

Paul D Madland

Rachael Jade Parker

Julien Sebot

Carlos Alfonso Tokunaga

Daniel J Ragland

Brent R Carlton

Zhongsheng Wang

Hung-Piao Ma

Lakshmipriya Seshan

Paul J Thadikaran

Ana M Yepes

Charles E Dike

Mark L Elzinga

Turbo Majumder

Whitney Michael Bryks

Arik Gihon

Jason A Mix

Tomer Levy

Narasimha Lanka

John Fallin

Eduardo Alban

Srinivas Venkata Ramanuja Pietambaram

Peter Sagazio

Gregory M Iovino

Michael C Rifani

Mohamed Abdelsalam

Thripthi Hegde

Amr M Lotfy

Navindra Navaratnam

Raymond Chong

Bee Min Teng

Ali M El-Husseini

Nasirul I Chowdhury

Timothy M Wilson

Jeffrey Krieger

R Tim Frodsham

Kandadai Ramesh

Mohammed W El Mahalawy

Allan Feldman

Ravindra B Venigalla

Mamdouh O Abd El-Mejeed

Yevgeni Sabin

Harishankar Sridharan

Minki Cho

Young Min Park

Ameya Ambardekar

Jagannadha Rao Rapeta

Monib Ahmed

Mike J Tripp

Peipei Wang

Surya Musunuri

Jacob Schneider

Anne Meixner

Yi Lu

Sarah E Bates

Amit Zeevi

Yingyu Miao

Michael Shusterman

Jeff Wight

Chaodan Deng

Eric Fetzer

Rajay R Pai

Pushkar Gorur

E Jeffrey Wight

Roman Rechter

Syed Feruz Syed Farooq

Maor Tal

Sarah Shahraini

Ishaan S Shah

An electronic device and associated methods are disclosed. In one example, the electronic device includes a MEMS die located within a substrate, and below a processor die. In selected examples, the MEMS die includes a resonator. Example methods of forming MEMS resonator devices are also shown.

Integrated MEMS resonator and method

An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

Frequency overshoot and voltage droop mitigation apparatus and method

Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.

Monitor circuitry for power management and transistor aging tracking

A clock buffer or driver is gated pending reception of verifiable crypto keys. These clock buffer or divers remain gated, thus disabling a processor from any meaningful function, till crypto keys are decoded, verified, and applied to the clock buffer or driver. A low frequency pseudorandom frequency hopping time sequence is generated and used for randomizing spread-spectrum to modulate a reference clock (or output clock) of a frequency synthesizer. This hopping time sequence holds the key to unlocking the crypto keys. The PWM modulated crypto keys are carried by the hopping time sequence. To decode the PWM modulated crypto keys, the hopping time sequence is used. The reference clock which is modulated with crypto keys in the spread-spectrum is sent to a decoder (in a processor) along with the hopping time sequence. The crypto keys are decoded and then used to un-gate the clock buffer.

Intellectual property security locking apparatus and method

A multi-feedback circuit that compares a duty cycle corrected reference clock f, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fwith approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.

Low power apparatus and method to multiply frequency of a clock

A wireless communication device for communicating across a wireless communication channel includes one or more processors configured to determine whether a further device is generating a radio frequency interference at an operating frequency; transmit a request message to the further device requesting the further device vacate the operating frequency based on the determination that the further device is generating radio frequency interference; receive a response message from the further device; and generate an instruction based on the response message.

Methods and devices for dynamically avoiding radio frequency interference

An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

Digitally coordinated dynamically adaptable clock and voltage supply apparatus and method

An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.

Apparatus for autonomous security and functional safety of clock and voltages including adjustment of a divider ratio

An apparatus and method to protect unauthorized change to a reference clock for a processor. The apparatus comprises: a first oscillator to generate a first clock; a second oscillator to generate a second clock; a third oscillator to generate a third clock; a first counter to count frequency of the first clock with respect to a fourth clock; a second counter to count frequency of the second clock with respect to the fourth clock; a third counter to count frequency of the third clock with respect to the fourth clock; and a circuitry to compare frequencies of the first, second, and third clocks with one another. The oscillators can be embedded in an interposer or package. These oscillators include one or more of: LC oscillator, micro electro-mechanical system (MEMs) based resonator, or ring oscillator.

Clock glitch mitigation apparatus and method

An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

Apparatus to improve lock time of a frequency locked loop

An apparatus is provided for low latency adaptive clocking, the apparatus comprises: a first power supply rail to provide a first power; a second power supply rail to provide a second power; a third power supply rail to provide a third power; a voltage divider coupled to the first, second, and third power supply rails; a bias generator coupled to voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.

Low latency analog adaptive clocking

An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

Data and clock synchronization and variation compensation apparatus and method

Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.

Self-referenced droop detector circuitry

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Portland, OR, United States of America

Nasser A Kurd