Emc Corporation

Sun Microsystems, Inc.

Emc Corporaration

Naser Marmash

Avinash Kallat

Brandon L Paul

Andrew Kniager

Mark Botello

Adam Peltz

An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Interrupt processing system

A simulation model for a system wherein data passes from a source domain to a destination domain, such source and destination domains operating with different, asynchronous clocks provided to the source and destination domains. The model includes a three-stage delay network fed by data from the source domain in response to clock provided to operate the source domain. The network operates in response to clocks provided to operate the destination domain. The model includes a selector having inputs fed by outputs of the three delays and an output fed to the destination domain, such selector randomly providing to the output of such selector outputs of the each of the delays from the three stage delay network. The selector output is randomly chosen only when the data in the source domain changes logical state from a logic low to high or from a logic high to low. Otherwise, if this were performed on every clock of the destination domain, the randomness would not be evenly distributed between all three-delay stages.

Method and apparatus for accurate modeling of multi-domain clock interfaces

Messages signaling interrupt (MSI) processing system

A system and method providing address broadcast synchronization using multiple switches. The system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch is configured to receive the address request from the first plurality of sources from the first switch. The second switch is further configured to delay the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch. The second switch selects a selected address request, and the first and the second switch are further configured to broadcast concurrently a corresponding address to the selected address request. A method is also contemplated for concurrently providing addresses to a plurality of devices. A method of arbitrating in a first switch and a second switch between requests to the first switch and the second switch is disclosed where the arbitrated outcomes in both the first switch and the second switch are identical.

System and method for address broadcast synchronization using a plurality of switches

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Ashland, MA, United States of America

Naser Marmash