Facebook, Inc.

Meta Platforms, Inc.

Intel Corporation

Advanced Micro Devices Corporation

Narsing Krishna Vijayrao

Giovanni Coglitore

Jason M Taylor

Christian Markus Petersen

Sudarshan Kumar

Kestutis Patiejunas

Keith Adams

Jay Parikh

Hongzhong Jia

Chi Keung Lee

William Alexander Hughes

Greggory D Donley

Kalyan Saladi

Jiann-Cherng James Lan

Mahadevamurty Nemani

Wenjie Jiang

Pallab Bhattacharya

Koh Yew Thoon

Jia Ning

Shobhit O Kanaujia

Domas Mituzas

David Sebastien Mortenson

Kevin Desmond Lee

Kumar Sudarshan

Mark Douglas Callaghan

A disclosed system may include a disaggregated artificial intelligence (AI) operation accelerator including a dense AI operation accelerator configured to accelerate dense AI operations and a sparse AI operation accelerator, physically separate from the dense AI operation accelerator, configured to accelerate sparse AI operations. The system may also include a scheduler that includes (1) a receiving module that receives an AI operation, (2) an identifying module that identifies the AI operation as a dense AI operation or sparse AI operation, and (3) a directing module that directs (a) the dense AI operation accelerator to accelerate identified dense AI operations, and (b) the sparse AI operation accelerator to accelerate identified sparse AI operations. The system may also include a physical processor that executes the receiving module, the identifying module, and the directing module. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for disaggregated acceleration of artificial intelligence operations

A disclosed system may include (1) a memory package having a physical memory and optical circuitry, (2) a processor package, separate and distinct from the memory package, having at least one physical processor and additional optical circuitry, and (3) an optical medium communicatively coupling the optical circuitry of the memory package with the additional optical circuitry of the processor package. Various other systems, apparatuses, and methods are also disclosed.

Systems having disaggregated components coupled by optical media

The disclosed computer-implemented method may include receiving, from a host via a cache-coherent interconnect, a request to access an address of a coherent memory space of the host. When the request is to write data, the computer-implemented method may include (1) performing, after receiving the data, a post-processing operation on the data to generate post-processed data and (2) writing the post-processed data to a physical address of a device-attached physical memory mapped to the address. When the request is to read data, the computer-implemented method may include (1) reading the data from the physical address of a device-attached physical memory mapped to the address, (2) performing, before responding to the request, a pre-processing operation on the data to generate pre-processed data, and (3) returning the pre-processed data to the external host via the cache-coherent interconnect. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for pre-processing and post-processing coherent host-managed device memory

The disclosed computer-implemented method may include (1) receiving, at a storage device via a cache-coherent interconnect, a first request to access data at one or more host addresses of a coherent memory space of an external host processor, (2) updating, in response to the first request, one or more statistics associated with accessing the data at the one or more host addresses, (3) receiving, at the storage device via the cache-coherent interconnect, a second request to perform an operation associated with the one or more statistics, and (4) using the one or more statistics to perform the operation. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for profiling host-managed device memory

The disclosed IC package may include (1) an IC die carrying electronic circuitry, (2) an encapsulation material that at least partially covers the IC die, where the encapsulation material defines a plurality of cavities in a top surface of the encapsulation material, (3) a plurality of microfans located in the plurality of cavities, and (4) a plurality of sensors embedded in the encapsulation material, where each sensor of the plurality of sensors produces a signal indicating a temperature at a location of the sensor. Various other IC packages, as well as associated cooling systems and methods, are also disclosed.

IC package with embedded fan-based cooling system

A first set of 64 bytes of data and a second set of 64 bytes of data are received. A first set of eight error-correcting code (ECC) bytes for the first set of 64 bytes of data and a second set of eight ECC bytes for the second set of 64 bytes of data are calculated. The first set of 64 bytes of data, the second set of 64 bytes of data, the first set of eight ECC bytes, and the second set of eight ECC bytes are sent to one or more 5generation double data rate (DDR) synchronous dynamic random-access memory (SDRAM) modules through a DDRdual-channel in a single burst, wherein the DDRdual-channel comprises a first data channel and a second data channel, and wherein the first data channel and the second data channel are driven by a same clock signal.

Reduced error correction code for dual channel DDR dynamic random-access memory

A controller device is disclosed. The controller device comprises a communication interface that is configured to receive a data operation request via an interconnect bus. The controller device comprises an integrated interconnect protocol component that is configured to handle communication via the interconnect bus that supports coherency across a plurality of different processing devices external to the controller device. An integrated memory or storage controller component on the same controller device is configured to handle the data operation request including by being configured to manage communication with a memory or data storage device external to the controller device.

Memory and storage controller with integrated memory coherency interconnect

An expansion card may include a printed circuit board and a hardware accelerator that is disposed on the printed circuit board. The hardware accelerator may include application-specific hardware circuitry designed to perform a computing task. The hardware accelerator may also offload a portion of the computing task from a central processing unit of a computing device by executing, via the application-specific hardware circuitry, the portion of the computing task. The expansion card may further include an edge connector, disposed on the printed circuit board, that is dimensioned to be inserted into an expansion socket of the computing device. The edge connector may couple the hardware accelerator to the central processing unit via a computing bus connected to the expansion socket. The edge socket may also include a pinout that is more compact than a pinout specification defined for the computing bus. Various other apparatuses, systems, and methods are also disclosed.

Apparatus, system, and method for performing hardware acceleration via expansion cards

An indication to share a content item associated with a residential cache appliance and a first social networking account is received. A network address of the residential cache appliance is associated with the content item. A cache map of available residential cache appliances is maintained to implement a distributed cache store. For one or more of the available residential cache appliances, the cache map identifies at least an associated social networking account, an associated network address, associated cache appliance stored content items, and an associated setting. From a requester device associated with a second social networking account, a request for the content item is received. In response to the request, based at least in part on the cache map, the requester device is directed to the residential cache appliance to obtain at least a portion of the content item.

Residential cache appliance utilizing a social network

A system and method for multi-channel communication with dual in-line memory modules ('DIMMs') is disclosed. The system retrieves information characterizing a plurality of memory channels, each of each is configurable to facilitate data communication between a DIMM and a memory controller with associated memory channel interfaces. Based on the retrieved information, one of the memory channels is designated as the active memory channel, granting the designated memory channel the ability to issue memory requests or transactions to the DIMM. On a periodic or as-needed basis (e.g., when the active memory channel is stalled or nearly stalled), the system determines whether to designate a different of the memory channels as the active memory channel, thereby enabling the newly-designated active memory channel the ability to issue memory requests or transactions to the DIMM. In some embodiments, only one of the memory channels is active at a time for communication with each DIMM.

Multi-channel DIMMs

Technology is provided for partitioning a shared unified cache in a multi-processor computer system. The technology can receive a request to allocate a portion of a shared unified cache memory for storing only executable instructions, partition the cache memory into multiple partitions, and allocate one of the partitions for storing only executable instructions. The technology can further determine the size of the portion of the cache memory to be allocated for storing only executable instructions as a function of the size of the multi-processor's L1 instruction cache and the number of cores in the multi-processor.

Partitioning shared caches

A method for performing client-side content inference may include (1) receiving a request to upload, from a client-side device to a server-side device, a content item that includes a first sequence of bytes and a second sequence of bytes, (2) identifying a model configured to output a classification for sequences of bytes, (3) using, at the client-side device, the model to derive a first classification for the first sequence, (4) using, at the client-side device, the model to derive a second classification for the second sequence, and (5) uploading, in response to the request, the content item to the server-side device by (a) uploading the first sequence, (b) uploading the first classification substantially contemporaneous with uploading the first sequence, (c) uploading the second sequence, and (d) uploading the second classification substantially contemporaneous with uploading the second sequence. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for performing client-side content inference

Embodiments are disclosed for managing a distributed data center. The managing can include receiving content interaction history associated with a first social networking account of a social networking system at a content distribution system; maintaining a cache map of available cache appliances to implement a distributed cache store; selecting a content item to push to a residential cache appliance based on the content interaction history, wherein pushing the content item includes updating the cache map to associate a network address of the residential cache appliance with an identifier of the content item; and providing a content distribution service configured to redirect a content streaming request for the content item to the residential cache appliance when the content item is determined to be available in the distributed cache store according to the cache map.

Growing community of inventors

Santa Clara, CA, United States of America

Narsing Krishna Vijayrao