Cirrus Logic Inc.

Crystal Semiconductor Corporation

Nariankadu Datatreya Hemkumar

Younes Djadi

Sachin Deo

Nathan Daniel Pozniak Buchanan

Shawn R McCaslin

Eric B Smith

Miroslav V Dokic

Bheeshmar Redheendran

Christopher Jackson

Daniel T Bogard

Raghunath Krishna Rao

Junsong Li

Sanjay Ramakrishna Pillay

Wai-Shun Shum

Vladimir Mesarovic

Akhilesh Persha

James P McFarland

Roshan Kamath

Brent W Wilson

John Camagna

Mandeep Chadha

Franz Weller

Vivek T Bhat

Jeffrey B Livingston

Nathan Buchanan

Ronald D Wiese

A method for dynamic configuration of a register map in an embedded software system may include, in response to receipt of configuration parameters for the register map, generating at least one table of metadata descriptors associated with objects of the register map based on the configuration parameters and embodied in random access memory of the embedded software system, the metadata descriptors defining composition and order of registers of the register map and configured to interface with a register map interpreter in firmware stored in read-only memory of the embedded software system.

Dynamically configurable firmware register map interface for an embedded software system

A system has a memory programmed with multiple firmware images each having an associated distinct entry point, a processor, a writable hardware register, and a controller external to the processor that, prior to each reset of a sequence of resets of the processor, reads the entry point of a firmware image from the hardware register and causes the processor to begin fetching instructions at the entry point read from the hardware register. The firmware images include boot, mission mode, and at least one other firmware image. The memory may be writeable with a modifiable version of a post-production mission mode, debug, prototype, or patched ROM firmware image. A second controller writes a second entry point to the hardware register prior to an initial reset such that the external controller reads the second entry point and causes fetching instructions at the second entry point rather than the initial entry point.

System with dynamically selectable firmware image sequencing for production test, debug, prototyping

A distributed processing system with multiple systems connected by an inter-system communication interface. Each system has a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable (by another system of the distributed processing system) hardware register initially seeded with an initial firmware image entry point, and a controller external to the processor that, prior to an initial reset, reads the entry point from the hardware register and causes the processor to begin fetching instructions at the initial entry point. Prior to a subsequent reset of the processor, the external controller facilitates a transition to another firmware image by reading its entry point from the hardware register and causing the processor to begin fetching instructions at the other entry point. Each system may have multiple processors and multiple associated hardware registers writeable by another processor of the system or a by host processor.

Multi-processor system with dynamically selectable multi-stage firmware image sequencing and distributed processing system thereof

A system includes primary and secondary devices (e.g., camera controllers that drive voice coil motors) each having respective outputs and a communication link. The primary device includes first and second hardware timers, each of which expires at a time derived from a periodic control loop trigger. At first timer expiration, the primary transmits first updated values to the secondary. At second timer expiration, primary device hardware picks up and applies second updated values to the primary device outputs. In response to receiving the first updated values from the primary device, the secondary device applies the received first updated values to its outputs. The primary/secondary device combination provide a sufficient number of total outputs that they could not individually provide and further synchronize the outputs with small skew through the timers, which are programmable to also accommodate processing of inputs (e.g., from voice coil motor sensors) to compute the outputs.

System and method for providing increased number of time synchronized outputs by using communicating primary and secondary devices

A system for using actuators to control an image sensor and/or lens based on sensor data received from position sensors and based on position information for the image sensor and/or lens received from a host processor includes a primary camera controller device, at least one secondary camera controller device, and at least one communication link connecting the primary camera controller device and the at least one secondary camera controller device. The primary and secondary camera controller devices receive respective primary and secondary sensor data from the position sensors, send the respective primary and secondary sensor data to the other camera controller device via the communication link, process the primary and secondary sensor data and the position information to generate respective primary and secondary control data, and drive the respective primary and secondary control data to the actuators concurrently.

Multi-chip camera controller system with inter-chip communication

A system for using actuators to control an image sensor and/or lens based on sensor data received from position sensors and position information for the image sensor and/or lens received from a host processor includes a primary camera controller device, at least one secondary camera controller device, and at least one communication link connecting the primary camera controller device and the secondary camera controller device. The primary camera controller device processes the received sensor data and the received position information to generate control data, sends a secondary portion of the control data to the secondary camera controller device via the communication link, and drives a primary portion of the control data to the actuators. The secondary camera controller device drives the received secondary portion of the control data to the actuators concurrently with the primary camera controller device driving the primary portion of the control data to the actuators.

A system includes a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable hardware register initially seeded with an initial firmware image entry point address. A controller external to the processor, prior to an initial processor reset, reads the hardware register and causes the processor to begin fetching instructions at the initial firmware image entry point read from the hardware register. Prior to a subsequent reset, the external controller facilitates at least one transition to at least one of the multiple firmware images other than the initial firmware image by reading the entry point of the other firmware images from the hardware register and causing the processor to begin fetching instructions at the entry point of the other firmware images read from the hardware register.

System with hardware register and controller external to processor that facilitates transitions between firmware images using hardware register written with firmware image entry points

A multicore processor may include a plurality of cores including at least a first core and a second core, a shared peripheral comprising a plurality of interrupt register banks including at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core, and a plurality of communications bridges, including at least a first bridge interfaced between the first core and the shared peripheral and at least a second bridge interfaced between the second core and the shared peripheral. The first core may be configured to program the first interrupt register bank via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second interrupt register bank via the second bridge to configure the shared peripheral for access by the second core.

Systems and methods for context-dependent multicore interrupt facilitation

A system may include a processing engine and an analog-to-digital conversion interface subsystem communicatively coupled to the processing engine. The processing engine may be configured to process feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate and based on processing of the feedback data, generate digital control signals for controlling a system under control. The analog-to-digital conversion interface subsystem may be configured to flexibly control the processing of the processing engine and the generation of digital control signals by the processing engine to minimize latency in the generation of the digital control signals due to processing of the processing engine.

Flexible latency-minimized delivery and management of disparate-rate data streams and sub-streams for processing

A system for atomically transferring vectors of data from a transmitter of the vectors of data to a receiver of the vectors of data may include a plurality of memory buffers configured to store the vectors of the data, each buffer configured to store one vector of the vectors of data at a time, the plurality of memory buffers comprising at least three memory buffers and a controller for controlling the plurality of memory buffers. The controller may be configured to, responsive to a condition for transferring information represented by the vectors of data to the receiver, determine which of the plurality of buffers from which the receiver may receive most-recently updated information completely written to the plurality of buffers by the transmitter. The controller may further be configured to, responsive to a condition for updating information represented by the vectors of data, determine which of the plurality of buffers for the transmitter to write updated information without blocking atomic receipt by the receiver of information from a most-recently updated buffer.

Flexible, non-blocking asynchronous transfer of time-variant atomic data

A system for reading a plurality of subset views of an evolving data store may include for each subset view, a plurality of memory buffers comprising at least three buffers. The system may also include control circuitry for controlling the plurality of memory buffers of the plurality of subset views, the control circuitry configured to maintain, for each subset view, a variable defining a most-recently updated buffer of the plurality of buffers such that a read request for such subset view will respond with data of the most-recently updated buffer of such subset view; and responsive to an update of data of the evolving data store: (i) determine, for each subset view, a selected data buffer of the plurality of buffers other than the most-recently updated buffer for such subset view to write updated subset view information; (ii) cause, for each subset view, the updated subset view information for such subset view to be written to the selected data buffer for such subset view; and (iii) substantially simultaneously across all of the plurality of subset views, update the variables defining the most-recently updated buffer of the plurality of subset views such that a subsequent read request for a subset view will respond with the updated subset view information for such subset view.

Discrete exchange and update of multiple consistent subset views of an evolving data store

A processor and processing method for reusing arbitrary sections of program code provides improved upgrade capability for systems with non-alterable read only memory (ROM) and a more flexible instruction set in general. A specific program instruction is provided in the processor instruction set for directing program execution to a particular start address, where the start address is specified in conjunction with the specific program instruction. An end address is also specified in conjunction with the specific program instruction and the processor re-directs control upon completion of code execution between the start and end address to either another specified address, or to a stored program counter value corresponding to the next instruction in sequence after the specific program instruction. A loop count may also be supplied for repeatedly executing the code between the start and end address until the count has expired.

Processor and processing method for reusing arbitrary sections of program code

A method of processing a stream of encoded units of data samples includes the step of calculating a sample advantage using timing information embedded in selected ones of the encoded units, the sample advantage representing a time difference in number of samples between the presentation of a reference sample and the availability of the reference sample. A number of phantom samples substantially equal to the number of samples represented by the calculated sample advantage are queued and then output from the queue at a selected rate. Substantially simultaneous with the outputting of the phantom samples from the queue, at least some data samples of at least one encoded unit are decoded and queued behind the phantom samples.

Methods and systems for prefilling a buffer in streaming data applications

A communication integrated circuit, such as a full-duplex speakerphone circuit, includes a double-talk detector that operates in combination with an echo canceller. The echo canceller includes an adaptive filter with filter coefficients that are regularly adjusted to train to a received echo. The double-talk detector includes an ERLE detector for measuring the current ERLE of the echo canceller and a logic circuit for determining a best ERLE value over a plurality of measurements. The double-talk detector also includes a power estimator and noise estimator for determining a noise level. The noise level attained when the ERLE value is the best ERLE value is saved as a benchmark noise level. Filter coefficients of the echo canceller are updated or updating is blocked based on several considerations including a comparison of ERLE value to best ERLE value, the noise level in comparison to the benchmark noise level, whether the circuit is operating in half-duplex or full-duplex mode, and detection of a tone.

Full-duplex speakerphone circuit including a double-talk detector

A method for synchronizing stream processing with a locally generated system time clock is disclosed. A program clock reference is recovered from a transport layer and used to vary the frequency of the locally generated system time clock. A presentation time stamp is recovered from a packetized elementary stream derived from the transport layer. The relationship between a reference sample associated with the presentation time stamp from the packetized elementary stream and a current sample being streamed is determined relative to the system time clock. Data samples are added or subtracted from a stream of data samples being streamed in response to the step of determining to establish a relationship between the stream of samples and the presentation time stamp relative to the system time clock.

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Austin, TX, United States of America

Nariankadu Datatreya Hemkumar