International Rectifier Corporation

Infineon Technologies Americas Corp.

Naresh Thapar

Adam I Amali

Michael A Briere

Daniel Marvin Kinzer

Chuan Cheah

Ling Ma

Kyle A Spring

Ashita Mirchandani

Donald He

Ritu Sodhi

Siddharth Kiyawat

Srini Thiruvenkatachari

Jianjun Cao

Timothy Donald Henson

Reenu Garg

Paul Harvey

David Kent

A transistor includes a source finger electrode having a source finger electrode beginning and a source finger electrode end. The transistor also includes a drain finger electrode with a curved drain finger electrode end having an increased radius of curvature. The resulting decreased electric field at the curved drain finger electrode end allows for an increased breakdown voltage and a more robust and reliable transistor.

Transistor having increased breakdown voltage

According to one exemplary embodiment, a rectifier circuit includes a diode. A first depletion-mode transistor is connected to a cathode of the diode. Also, at least one second depletion-mode transistor is in parallel with the first depletion-mode transistor and is configured to supply a pre-determined current range to a cathode of the diode. A pinch off voltage of the at least one second depletion-mode transistor can be more negative than a pinch off voltage of the first depletion-mode transistor and the at least one second depletion-mode transistor can be configured to supply the pre-determined current range while the first depletion-mode transistor is OFF. Also, the pre-determined current range can be greater than a leakage current of the first depletion-mode transistor.

High voltage rectifier and switching circuits

There are disclosed herein various implementations of a transistor having a segmented gate region. Such a transistor may include at least one segmentation dielectric segment and two or more gate dielectric segments. The segmentation dielectric segment or segments are thicker than the gate dielectric segments, and is/are situated between the gate dielectric segments. The segmentation dielectric segment or segments cause an increase in the effective gate length so as to improve resistance to punch-through breakdown between a drain electrode and a source electrode of the transistor when the transistor is off.

Power transistor having segmented gate

An accumulation mode FET (ACCUFET) having a source contact that makes Schottky contact with the base region thereof.

ACCUFET with Schottky source contact

A trench power semiconductor device including a recessed termination structure.

Trench MOSFET technology for DC-DC converter applications

An accumulation mode FET (ACCUFET) which includes an insulated gate, an adjacently disposed insulated source field electrode, and a source contact that makes Schottky contact with the base region of the ACCUFET.

A power semiconductor device which includes a source field electrode, and at least one insulated gate electrode adjacent a respective side of the source field electrode, the source field electrode and the gate electrode being disposed in a common trench, and a method for fabricating the device.

MOSgated power semiconductor device with source field electrode

ACCUFET with schottky source contact

A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

Trench fet with self aligned source and contact

Trench FET with self aligned source and contact

A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low Rand increased Vand Vand a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 &#x212b; to 1400 &#x212b; and the nitride is subsequently removed and a thin oxide, for example 320 &#x212b; is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon. A very lightly doped diffusion of 1000 &#x212b; to 2000 &#x212b; in depth could also be formed around the bottom of the trench and is depleted at all times by the inherent junction voltage to further reduce Miller capacitance and switching loss.

Low voltage power MOSFET device and process for its manufacture

A process for manufacturing a semiconductor device of the trench variety with reduced feature sizes and improved characteristics which process includes forming a termination structure having a field oxide disposed in a recess below the surface of the semiconductor die in which the active elements of the device are formed, and forming source regions after the major thermal steps have been performed.

Method for manufacturing a semiconductor device with a trench termination

A MOSgated device has spaced vertical trenches lined with a gate oxide and filled with a P type polysilicon gate. The gate oxide extends along a vertical Nchannel region disposed between an Nsource region and an Ndrift region. A Schottky barrier of aluminum is disposed adjacent the accumulation region extending along the trench to collect holes which are otherwise injected into the source region during voltage blocking. A common source or drain contact is connected to the Nregion and to the Schottky contact. A two gate embodiment is disclosed in which separately energized gates are connected to alternatively located gate polysilicon volumes.

Growing community of inventors

Redondo Beach, CA, United States of America

Naresh Thapar