Cadence Design Systems, Inc.

Sentiss Pharma Private Limited

Delhi Institute of Pharmaceutical Sciences and Research (dipsar)

Naresh Kumar

Prashant Sethia

Umesh Gupta

Amit Dhuria

Sushobhit Singh

Rakesh Agarwal

Arvind Nembili Veeravalli

Sneh Saurabh

Ritika Govila

Manuj Verma

Pradeep Yadav

Ankit Sethi

Shashank Tripathi

Marut Agarwal

Manish Bansal

Jayant Sharma

Beenish

Igor Keller

Krishna Prasad Belkhale

Deepak Bahri

Shagufta Siddique

Jeannette Sutherland

Ratnakar Goyal

Vishnu Kumar

Ankur Gulati

Shashank Prasad

Lalit Bharat

Suresh Kumar Gupta

Shyam Sunder Agrawal

Renu Agrawal

Sushma Srivastava

Vishal Karda

Ankita Nagpal

Rohit Saxena

Sateesh Kumar Chauhan

Harindranath Parmeswaran

Mahesh Diwakar Sadhankar

Hemendra Singh Negi

Arunjai Singh

Daksh Bakshi

Mahesh D Sadhankar

Shubham Kumar

Satyendra Patel

Sourabh Kumar Verma

Sukriti Khanna

Ajay Tomar

Puneet Munjal

Kaustav Guha

Vipul Parikh

The present disclosure relates to a system and method for electronic design automation. Embodiments may include loading one or more libraries, netlists, or constraints associated with an electronic design and loading parasitic data associated with the electronic design. Embodiments may further include performing a self adaptive, infinite depth, path based analysis on at least a portion of the electronic design. Embodiments may also include analyzing the electronic design based upon, at least in part, the self adaptive, infinite depth, path based analysis.

Adaptive path based analysis process

Embodiments include herein are directed towards a method for automatic detection during a timing analysis. Embodiments may include reading, using a processor, design and power intent information associated with an electronic design and automatically identifying a plurality of inter-power domain paths from the design and power intent information. Embodiments may further include automatically filtering the plurality of inter-power domain paths to identify one or more faulty inter-power domain paths using a graph-based approach and automatically generating a report depicting the one or more faulty inter-power domain paths.

System and method for automatic fault detection in an electronic design

A static timing analysis system for finding and reporting timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use exhaustive path-based analysis (EPBA) that is informed by infinite-depth path-based analysis (IPBA) to provide analysis results that are driven full-depth, in contrast to conventional EPBA systems and methods, which can terminate after reaching a maximum depth of analysis as a way of avoiding prolonged or infinite runtimes. The IPBA-driven full-depth EPBA functions for hold-mode as well as setup-mode analysis and achieves reduced pessimism as compared to systems or methods employing IPBA alone, and more complete analysis of designs as compared to systems or methods employing EPBA alone. Improved IPBA signal merging using multidimensional zones for thresholding of signal clustering mitigates the occasional optimism of IPBA.

IPBA-driven full-depth EPBA of operational timing for circuit design

Embodiments include herein are directed towards a method for static timing analysis. Embodiments included herein may include providing, using at least one processor, a database of predefined script tags and causing a display of a script at a graphical user interface. Embodiments may also include receiving an insertion of at least one tag from the database within the script and generating one or more timing reports based upon, at least in part, the script and the at least one tag.

System and method for performing static timing analysis of electronic circuit designs using a tag-based approach

Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.

System and method for performing sign-off timing analysis of electronic circuit designs

The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving an electronic design having a plurality of objects associated therewith. Embodiments may further include allowing, at a graphical user interface, a user to define at least one user-refined filter selected from the group consisting of an instance pin filter, a library cell instance filter, a clock pin filter, and a net filter. Embodiments may also include generating one or more constraints based upon, at least in part, the user-refined filter.

System and method for objective probing and generation of timing constraints associated with an electronic circuit design

The present embodiments relate to static timing analysis (STA) of circuits. The STA can include determining graph based analysis (GBA) delays of timing paths within the circuit. Path based analysis (PBA) delays of a subset of timing paths can be determined to generate circuit stage credit values for circuit stages in the circuit. The circuit stage credit values can be used to adjust GBA delays of the timing paths. Prediction functions can be utilized to predict or estimate PBA delays of timing paths thereby avoiding the determination of actual PBA delays of the timing paths.

Circuit stage credit based approaches to static timing analysis of integrated circuits

The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include providing, using at least one processor, an electronic design and extracting hierarchical crossing path exception information from a hierarchical design view associated with the electronic design. Embodiments may further include transferring the hierarchical crossing path exception information to a block view associated with the electronic design and extracting a timing model based upon, at least in part, the hierarchical crossing path exception information. Embodiments may also include implementing the timing model at a top-level view associated with the electronic design.

Systems and methods for extracting hierarchical path exception timing models

A static timing analysis system for finding timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use infinite-depth path-based analysis (IPBA) to achieve reduced pessimism as opposed to systems or methods employing only graph-based analysis (GBA), but with greatly reduced compute time requirements, or greater logic path coverage, versus systems or methods employing conventional or exhaustive path-based analysis. IPBA achieves the improved coverage or compute time results by slotting nodes of a circuit design graph into stages, propagating phases stage-by-stage for all paths in parallel, and merging phases wherever possible during the analysis.

Infinite-depth path-based analysis of operational timing for circuit design

A view definition analyzer maps a plurality of timing views for a circuit design into compatibility groups having shared operating conditions of their respective process corners. An ETM generator then extracts an extracted timing model from a block of the circuit design for each compatibility group, containing timing arcs representing each combination of interface path in the circuit block and timing view in the compatibility group, where at least one timing arc in the ETM is a merged version of multiple timing arcs for an interface path across multiple timing views in the compatibility group. Timing arcs are merged when each timing characteristic in a first timing arc matches, within a tolerance threshold, a corresponding timing characteristic in a second timing arc. The ETM may then be used to model any timing view in the compatibility group. The ETM generator thus produces a minimal set of extracted timing models.

Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs

A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.

Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic

The present disclosure relates to a system and method for electronic design automation. Embodiments may include receiving, using at least one processor, an electronic design and determining one or more graph based analysis ('GBA') violating nodes associated with the electronic design. Embodiments may include identifying a non-covered violating node from the GBA violating nodes and determining a worst timing path through the non-covered violating node. Embodiments may further include invoking a path-based analysis ('PBA') on the worst timing path and determining if the worst timing path satisfies the PBA analysis.

Comprehensive path based analysis process

For a circuit path to be represented in a timing model, a set of propagating waveforms substantially converges through waveform stabilization to a uniform waveform at a waveform invariant node and all pins following. The circuit path is decomposed at the waveform invariant node into first and second portions, which are characterized as first and second timing arcs. In computing output slew and delay values, the first timing arc generation factors only a single output load of the waveform invariant node, and the second timing arc generation factors only the uniform waveform. Similarly, a setup arc employs the uniform waveform rather than multiple clock input waveforms in computing setup/hold values. Simulation of waveform propagation is also simplified by simulating only the uniform waveform for the second portion. Additionally, the first arc may be shared between a plurality of circuit paths which share an input pin and the waveform invariant node.

Method and apparatus for efficient generation of compact waveform-based timing models

Disclosed is an improved approach to implement timing signoff and optimization. Integrated MMMC timing closure functionality is provided in a single software session. The system provides the capability to perform signoff analysis, debugging, ECO, and TSO optimization for a large number of MMMC views in single software session.

Method and system for performing distributed timing signoff and optimization

Methods and systems provide setup and generation of SPICE results for a set of timing path(s) and integration of SPICE simulation with static timing analysis (STA) path-based results generation. In an embodiment, a method may select a candidate set of timing paths, perform path based analysis (PBA) on the selected paths, generate SPICE results for the selected paths, and render the PBA and SPICE results in an integrated user interface to facilitate sign off based on annotated constraints and correlation between STA results and SPICE results. Methods and systems of the present disclosure find application in, among other things, timing signoff in an electronic design and verification process.

Method and apparatus for integrating spice-based timing using sign-off path-based analysis

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Noida, India

Naresh Kumar