Intel Corporation

Naresh K Sehgal

Rajesh K Gupta

Phani K Saripella

Sudhakar S Kale

Amit Chowdhary

Katalin Klara Bartfai-Walcott

Vasudevan Srinivasan

Mrittika Ganguli

Slawomir Putyrski

Arkadiusz Berent

David Novick

Vasuki Chilukuri

Mark P Baldwin

Bartosz Gotowalski

Artour Levin

Arkadiusz Chylinski

Marek Jakowski

Miles F McCoo

Kiran Ganesh

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) for software defined silicon security are disclosed. Example apparatus include a trusted agent determiner to (i) determine respective reputation scores associated with a plurality of agents in a mesh network, the plurality of agents associated with a plurality of semiconductor devices, respective ones of the semiconductor devices including circuitry configurable to provide one or more features, and (ii) select, based on the respective reputation scores, a first agent from the plurality of the agents to transmit a request to activate or deactivate at least one of the one or more features. Example apparatus also include an agent interface to, in response to the request, broadcast an activation or deactivation of the least one of the one or more features to the mesh network to cause the trusted agent determiner to update the reputation score of the first agent.

Systems, methods, and apparatus for software defined silicon security

Technologies for adjusting server power consumption include a computing device to receive resource utilization data from a plurality of servers. The computing device identifies a source server and a destination server of the plurality of servers based on the resource utilization data and calculates the difference in resource utilization between the identified source server and the identified destination server based on the resource utilization data. If the computing device determines that the difference exceeds a threshold value, the computing device increases processor utilization of a processor of the source server by a power consumption change amount and decreases processor utilization of a processor of the destination server by a corresponding power consumption change amount to balance the servers' resources and create more head-room to place new workloads on the servers.

Power balancing to increase workload density and improve energy efficiency

In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design. A vector is a group of template instances that are identical in function and in structure. The vectors generated by the structural regularity extraction component are used by a floorplanning component. The floorplanning component provides a method of generating a circuit layout from the set of vectors. In some embodiments, each vectors corresponds to a row in the circuit layout.

Structural regularity extraction and floorplanning in datapath circuits using vectors

A 2-dimensional placement system and method minimize reliability concerns arising from electromigration and self-heat while at the same time achieving a high layout density. The 2-dimensional placement method also uses a placement space with rows that have non-uniform sizes and are overlapping. According to one embodiment of the present invention, a computerized method of creating a layout for a circuit design includes receiving a circuit design and receiving at least one layout rule based on a reliability verification constraint for the circuit design. The computerized method further includes generating a layout for the circuit design through computer automated operations wherein the layout generated satisfies the at least one layout rule based on the reliability verification constraint received for the circuit design.

2-dimensional placement with reliability constraints for VLSI design

In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design. A vector is a group of template instances that are identical in function and in structure. The vectors generated by the structural regularity extraction component are used by a floorplanning component. The floorplanning component provides a method of generating a circuit layout from the set of vectors. In some embodiments, each vectors corresponds to a row in the circuit layout.

In some embodiments, the invention includes a method of regularity extraction including generating a set of templates for a circuit through computer automated operations on a description of the circuit. The method also includes covering the circuit with instances of a subset of the templates. In some embodiments, the set of templates includes single-principal output templates, where a single-principal output templates is a template in which all outputs of the template are in the transitive fanin of a particular output of the template. The set of templates may also include tree templates. In some embodiments, the set of templates is a complete set of templates given certain assumptions including that the set of templates include all maximal templates of involved classes of templates and a template is not generated through permuting gate inputs. In some embodiments, the covering of the circuit involves selecting one of the set of templates and meeting certain criteria and deleting all nodes in instances of the selected template. The covering may further include deleting the templates in the set of templates other than the selected templates and regenerating a new set of templates from the remaining uncovered circuit.

Systematic approach for regularity extraction

Growing community of inventors

Santa Clara, CA, United States of America

Naresh K Sehgal