Stmicroelectronics Gmbh

Interdigital Patent Holdings, Inc.

Vid Scale, Inc.

Naresh H Soni

Ariela Zeira

Yuriy Reznik

Yan Ye

Eldad M Zeira

Liangping Ma

Samian Kaur

Dimitrios Karampatsis

Gregory S Sternberg

Hang Liu

Eduardo Asbun

Weimin Liu

David L Isaman

Zhifeng Chen

Avi Rapaport

Described herein are methods and systems associated with viewing condition adaption of multimedia content. A method for receiving multimedia content with a device from a network may include determining a viewing parameter, transmitting a request for the multimedia content to the network, whereby the request may be based on the viewing parameter, and receiving the multimedia content from the network, whereby the multimedia content may be processed at a rate according to the viewing parameter. The viewing parameter may include at least one of: a user viewing parameter, a device viewing parameter, or a content viewing parameter. The method may further include receiving a multimedia presentation description (MPD) file from the network. The MPD file may include information relating to the rate of the multimedia content and information relating to the rate may include a descriptor relating to the viewing parameter, whereby the descriptor may be required or optional.

Methods and systems for video delivery supporting adaptation to viewing conditions

Methods, apparatuses and systems for performing hierarchical traffic differentiation and/or employing hierarchical traffic differentiation are provided. These methods, apparatuses and systems may be implemented to, for example, handle congestion and/or to manage user quality of experience (QoE). Performing the hierarchical traffic differentiation may include differentiating or otherwise classifying (collectively 'differentiating') traffic mapped to, or within, a bearer formed in accordance with a QoS class into multiple traffic sub-classes. Employing the hierarchical traffic differentiation may include scheduling and/or policing (e.g., filtering) the differentiated traffic for transmission based on a prioritization of, and/or policy for managing, the multiple traffic sub-classes.

Hierarchical traffic differentiation to handle congestion and/or manage user quality of experience

A data processing system having a distributed reservation station is provided which stores basic blocks of code in the form of microprocessor instructions. The present invention is capable of distributing basic blocks of code to the various distributed reservation stations. Due to the smaller number of entries in the distributed reservation stations, the look up time required to find a particular instruction is much less than in a centralized reservation station. Additional instruction level parallelism is achieved by maintaining single basic blocks of code in the distributed reservation stations. With a distributed reservation station, an independent scheduler can be used for each one of the distributed reservation stations. When the instruction is ready for execution, the scheduler will remove that instruction from the distributed reservation station and queue that instruction(s) for immediate execution at the particular execution unit. Multiple independent schedulers will provide greater efficiency when compared to a single scheduler which must contend with approximately 20-24 instructions that have increased dependency on one another.

Reservation stations to increase instruction level parallelism

The present invention utilizes a &ldquo;virtual&rdquo; condition code (VCC) which can control the instruction sequence in a microprocessor. The virtual condition code is stored in an internal, non-architected register that is not visible to the programmer, but is used by various microprocessor instructions to determine when a branch is to be taken. For example, the virtual condition code can be used as a condition for branching out of a series of repetitive instructions. The virtual condition code (VCC) can eliminate a portion of the processing overhead used when determining whether a sequential number, such as a count value in a register associated with a repetitive instruction, e.g. a LOOP, is zero. In accordance with one aspect of the present invention, a LOOP instruction will decrement a count value in a register (to maintain compatibility with the ISA). However, a corresponding branch instruction will use the virtual condition code, rather than checking the contents of the entire register, to determine whether or not to branch. In this manner, the present invention improves performance by minimizing the amount of hardware resources (i.e. compare logic) utilized while maintaining compatibility with the Intel architecture since the programmer visible condition code is not used. By leaving the programmer visible condition codes unchanged, the software is not forced to save and restore the register contents during each iteration.

Virtual condition codes

A system and method is provided to reduce the latency associated with saving and restoring the state of the floating point registers in a microprocessor when switching tasks between floating point and MMX operations, or between tasks within the same context. The present invention maintains a secondary register file along with the primary floating point register file in the CPU. The primary register will keep the state of the floating point task &ldquo;as is&rdquo; upon the occurrence of a task switch to MMX, or another context. The address of the area where the FPU state is saved is maintained in a save area address register. The secondary register is then utilized by the other context to store intermediate results of executed instructions. In the majority of cases when a context switch back to floating point operations occurs, the previous state is restored from the primary register without incurring the latency of retrieving the instructions and data from the memory subsystem. In addition to the secondary register, a snooping mechanism will use the address of the state save area to determine if the state save area was modified. If the state save area is modified, then the floating point state must be restored from the memory subsystem in a conventional manner. However, the floating point save area will seldom be modified and the penalty for maintaining the floating point state in the CPU is negligible. Further, the present invention will allow the microprocessor to operate in a compatible manner with current operating systems and application software.

System and method of saving and restoring registers in a data processing system

The present invention utilizes a cache which stores various decoded instructions, or parcels, so that these parcels can be made available to the execution units without having to decode a microprocessor instruction, such as a CISC instruction, or the like. This increases performance by bypassing the fetch/decode pipeline stages on the front end of the microprocessor by using a parcel cache to store previously decoded instructions. The parcel cache is coupled to the microprocessor fetch/decode unit and can be searched during an instruction fetch cycle. This search of the parcel cache will occur in parallel with the search of the microprocessor instruction cache. When parcel(s) corresponding to the complex instruction being fetched are found in the parcel cache a hit occurs and the corresponding micro-ops are then sent to the execution units, bypassing the previous pipeline stages. The parcel cache is dynamic and will use a replacement algorithm, such as least recently used, to determine how long the parcels will remain in the cache.

Parcel cache

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La Jolla, CA, United States of America

Naresh H Soni