Intel Corporation

Narendra S Khandekar

Zohar Bogin

Michael W Williams

Kuljit Singh Bains

Jasmin Ajanovic

James M Dodd

Howard S David

Steve John Clohset

Vincent E VonBokern

Ashish S Gadagkar

Aniruddha Kundu

David D Lent

Dahmane Dahmani

Robert F Kubick

Manish Muthal

John B Halbert

Vincent Edward Von Bokern

Robert N Murdoch

Robert M Ellis

Chris B Freeman

Kenneth C Holland

Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

Memory buffer device integrating refresh logic

A method of controlling power states in a memory device includes determining if a power-down command is received. A first lower power state is entered if the power-down command is received and the memory device is in a first state. A second lower power state is entered if the power-down command is received and if the memory device is in a second state. The second lower power state is lower than the first lower power state. The memory device remains in a normal operation power state if the power-down command is not received.

Method and apparatus for controlling power states in a memory device utilizing state information

Methods and apparatus for a memory system using line termination circuits in each memory unit (e.g., integrated circuit memory device) are disclosed. The memory unit contains termination control logic that sets the state of a controllable termination circuit to control reflections on the data bus. The termination control logic determines the proper state for the termination circuit from the state of its memory unit, and in some cases, from the approximate state of the data bus as gleaned from commands decoded from the command/address bus. A termination configuration register on the unit can be used to define the appropriate termination state for each unit state and/or data bus state.

Memory bus termination with memory unit having termination control

An apparatus and a method to track command signal occurrence for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes an interface to couple to a data bus, the data bus to transfer data between the interface and one or more memory devices, and a logic unit to generate a command occurrence signal to identify when a command signal is issued, wherein a set of data transfer operations on one of the one or more memory devices are completed in response to the command occurrence signal, a transition of a flag signal, and a chip select signal corresponding to the one memory device. Other embodiments have been claimed and described.

Apparatus and method to track command signal occurrence for DRAM data transfer

A method and an apparatus to track transition of a flag signal for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes one or more memory devices, coupled to a data bus, to receive a command signal, wherein the command signal initiates a set of data transfer operations to transfer data between the data bus and one of the one or more memory devices; and a timing unit, coupled to the one or more memory devices, to receive the command signal, a flag signal, and a memory select signal, the timing unit to generate a trigger signal, in response to a transition of the flag signal, to complete the data transfer operations if the memory select signal corresponds to the one of the one or more memory devices. Other embodiments have been claimed and described.

Apparatus and method to track flag transitions for DRAM data transfer

A method of addressing a memory device on a memory module includes determining whether a command has been issued to the memory module. An evaluation state is entered if the command has been issued. While in the evaluation state, it is determined whether an identification signal has been issued for the memory device to initiate action. Action is initiated if the identification signal indicates that the memory device is to respond to the command issued.

Method of addressing individual memory devices on a memory module

A technique to encode a precharge command on a flag signal used to execute data transfer to and from a DRAM.

Apparatus and method for encoding auto-precharge

Memory modules, memory systems, and computing devices are described which include memory buffer devices that buffer signals of memory devices. In some embodiments, the memory buffer devices are positioned to reduce the circuit board footprint of the memory buffer devices.

Memory buffer arrangement

Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices

A computer system that includes at least two host agents is provided. The computer system further includes a chipset that includes a resource to be shared by the at least two host agents. The chipset is coupled to the-at least two host agents. The chipset prevents a first host agent, that occupies the shared resource to access the shared resource until a second host agent, has made progress in accessing said shared resource.

Method and apparatus for resource sharing in a multi-processor system

A computer system that includes a host processor (HP), a system memory (SM), and a host bridge coupled to the HP and SM is provided. The host bridge asserts a first read request to the SM and, prior to availability of snoop results in connection with the first read request, the host bridge asserts a following second read request to the SM.

Speculative request pointer advance for fast back-to-back reads

According to one embodiment, a computer system is disclosed. The computer system includes a processor, a memory, an inverting device, a storage device coupled to the inverting device and a device coupled to the storage device. The device receives byte enable information and inverted information and provides inverted byte enable information to the memory upon a write back operation to the memory.

Apparatus and method for maintaining cache coherency in a memory system

A method and an apparatus for a synchronous DRAM-type memory control is provided that allows continued and accurate data transfer to and from a synchronous DRAM (syncDRAM) memory for special cases where data is not ready to be transferred. In the event that data is not ready to be transferred between a destination device and the syncDRAM, transfer of data is suspended. Concurrently, at the address from which data was not ready to be transferred, the address is latched by a syncDRAM interface that communicates with the system memory control and the syncDRAM memory. In the event of a read cycle, back-to-back read requests are performed until data can be transferred. In the event of a write request, a mask command is asserted to mask out the data address in the syncDRAM until data is ready to be written to the address, wherein the write request is then reasserted. For both read and write cycles, when data is subsequently ready to be transferred, data transfer is resumed at the latched address. This effectively replaces the clock enable functionality and provides cost savings and die size savings.

Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus

An embodiment of the invention is directed at a bridge having an outbound pipe for buffering transaction information and data being transported from various devices to a bus. The bridge has an arbiter for granting requests associated with these devices to access the outbound pipe for transferring the transaction information and data into the pipe. The bridge generates a reject signal in response to an initial request associated with an initial transaction from a first one of the devices if the outbound pipe is unavailable to accept further transaction information or data. The bridge has response control logic for generating a retry response for the initial transaction in response to the reject signal. The bridge is able to assert a stamp signal in response to the reject signal. The arbiter in response to the stamp being asserted waits, without granting any other lower priority requests to access the outbound pipe, until a subsequent transaction from the first device makes progress.

Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge

A method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus is described. In one embodiment, the method includes detecting a write cycle by an initiator for transmitting data to a device. The method further includes asserting a write request to the device, responsive to detecting the write cycle, asserting a ready request to the initiator without detecting an acknowledge from the device, and receiving the data from the initiator.

Growing community of inventors

Folsom, CA, United States of America

Narendra S Khandekar