Agere Systems Inc.

Intel Corporation

Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Narender R Vangati

David Sonnier

William G Burroughs

Te Khac Ma

Stephen Miller

Tsung-Yuan Charles Tai

Ren Wang

Andrew J Herdrich

Debra Bernstein

Jr-Shian Tsai

Stephen R Van Doren

Hugh Wilkinson

Niall D McDonnell

Deepak Mital

Yipeng Wang

Andrew Cunningham

Bruce Richardson

James T Clee

Jerry Pirog

Joseph R Hasting

Gage Eads

Jonathan Kenny

An Yan

Jamison D Whitesell

Edwin Verplanke

Bradley A Burres

Namakkal N Venkatesan

Rajarshi Bhattacharya

Robert J Munoz

Mauricio Calle

Vinoj Narayan Kumar

Steven J Pollock

Betty Ann McDaniel

James Thomas Kirk

Abraham Prasad

Larry Stephen King

Prachi Kale

William Edward Baker

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ('LLC'), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Multi-core communication acceleration using hardware queue device

Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

Technologies for a distributed hardware queue manager

An apparatus includes a memory and a processor. The memory may be configured to store at least a portion of a multi-level tree representation of an ordered multi-field rule-based classification list. The tree representation includes at least one non-leaf level and one or more leaf levels. Each entry in the at least one non-leaf level contains a count value indicating a number of rules having a matching field. Entries in at least one of the one or more leaf levels include rule pointers arranged in priority order. The processor may be configured to incrementally insert or delete rules, while preserving ordering semantics of the tree representation.

Incremental updates for ordered multi-field classification rules when represented by a tree of longest prefix matching tables

Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.

Network communications processor architecture

Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes instructions by fetching an instruction of the thread from an instruction memory of the packet classifier and determining whether a breakpoint mode of the network processor is enabled. If the breakpoint mode is enabled, and breakpoint indicator of the fetched instruction is set, the packet classifier enters a breakpoint mode. Otherwise, if the breakpoint indicator of the fetched instruction is not set, the multi-thread instruction engine executes the fetched instruction.

Instruction breakpoints in a multi-core, multi-thread network communications processor architecture

Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.

Reducing data read latency in a network communications processor architecture

Techniques are disclosed for generating a representation of an access control list, the representation being utilizable in a network processor or other type of processor to perform packet filtering or other type of access control list based function. A plurality of rules of the access control list are determined, each of at least a subset of the rules having a plurality of fields and a corresponding action, and the rules are processed to generate a multi-level tree representation of the access control list, in which each of one or more of the levels of the tree representation is associated with a corresponding one of the fields. At least one level of the tree representation other than a root level of the tree representation comprises a plurality of nodes, with at least two of the nodes at that level each having a separate matching table associated therewith.

Access control list constructed as a tree of matching tables

Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of managing data structures associated with code executable on a packet processor includes the following steps. Data structures in the code are identified as being one of static data structures and non-static data structures, wherein a static data structure includes a data structure that is not changed during execution of the packet processor code and a non-static data structure includes a data structure that is changed during execution of the packet processor code. One or more data structures associated with the packet processor code are managed in a manner specific to the identification of the one or more data structures as static data structures or non-static data structures. At least a portion of the data structures may include tree structures.

Methods and apparatus for updating data structures during in-service upgrade of software in network processor

Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of performing an in-service upgrade of code, storable in a memory associated with a packet processor and executable on the packet processor, from a first code version to a second code version, includes the following steps. A first step includes preparing for the upgrade by generating one or more write operations to effectuate the code upgrade from the first code version to the second code version. A second step includes updating the code from the first code version to the second code version by propagating the one or more write operations to the packet processor. A third step includes cleaning up after the updating step by reclaiming one or more memory locations available after the update step. As such, the storage of only a single version of the code in the memory associated with the packet processor is required.

Methods and apparatus for performing in-service upgrade of software in network processor

Techniques are disclosed for generating a representation of an access control list, the representation being utilizable in a network processor or other type of processor to perform packet filtering or other type of access control list based function. A plurality of rules of the access control list are determined, each of at least a subset of the rules having a plurality of fields and a corresponding action. The rules are processed to generate a multi-level tree representation of the access control list, in which each of one or more of the levels of the tree representation is associated with a corresponding one of the fields. At least one level of the tree representation comprises a plurality of nodes, with two or more of the nodes of that level having a common subtree, and the tree representation including only a single copy of that subtree. The tree representation is characterizable as a directed graph in which each of the two nodes having the common subtree points to the single copy of the common subtree.

Directed graph approach for constructing a tree representation of an access control list

A decision tree, representing a knowledge base, is segmented into at least two decision tree portions. The lower portion includes the tree entry point and is stored in a memory element with a faster access time than the upper portion, which includes the terminating element of the decision tree. Thus during the process of reading the tree entries for comparing them with the search object, the search entries in the lower portion of the tree can be read faster than the search entries in the upper portion, resulting in a faster traversal through the entire decision tree.

Method of improving the lookup performance of three-type knowledge base searches

A processing system includes a processing device and a host processor operatively coupled to the processing device via a system bus, and implements a scatter gather data transfer technique. The host processor is configurable to control the transfer of information to or from scattered or non-contiguous memory locations in a memory associated with the processing device, utilizing a data structure comprising a single descriptor. An information transfer bandwidth of the system bus is thereby more efficiently utilized than if a separate descriptor were used for transfer of information involving each of the non-contiguous memory locations.

Single descriptor scatter gather data transfer to or from a host processor

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Round Rock, TX, United States of America

Narender R Vangati