Texas Instruments Corporation

Fujitsu Corporation

Narendar M Shankar

Erdal Paksoy

Aymeric S Vial

Mehdi-Laurent Akkar

Gregory Remy Philippe Conti

Todd Vanyo

Steven C Goss

Sven-Inge Redin

Steven Charles Goss

Charles W Brokish

Olivier Schuepbach

Steve Karouby

Gregory R Conti

Jonathan Russell Agre

Yannis Labrou

Zhexuan Song

Jerome Laurent Azema

Ryusuke Masuouka

Wei-Iun Chen

Michael Grove

Derrill Sturgeon

A secure demand paging system () includes a processor () operable for executing instructions, an internal memory () for a first page in a first virtual machine context, an external memory () for a second page in a second virtual machine context, and a security circuit () coupled to the processor () and to the internal memory () for maintaining the first page secure in the internal memory (). The processor () is operable to execute sets of instructions representing: a central controller (), an abort handler () coupled to supply to the central controller () at least one signal representing a page fault by an instruction in the processor (), a scavenger () responsive to the central controller () and operable to identify the first page as a page to free, a virtual machine context switcher () responsive to the central controller () to change from the first virtual machine context to the second virtual machine context; and a swapper manager () operable to swap in the second page from the external memory () with decryption and integrity check, to the internal memory () in place of the first page.

Methods, apparatus, and systems for secure demand paging and paging operations for processor devices

An integrated circuit () includes an on-chip boot ROM () holding boot code, a non-volatile security identification element () having non-volatile information determining a less secure type or more secure type, and a processor (). The processor () is coupled to the on-chip boot ROM () and to the non-volatile security identification element () to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element (). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.

Less-secure processors, integrated circuits, wireless communications apparatus, methods for operation thereof, and methods for manufacturing thereof

A secure demand paging system including a secure internal memory, an external non-volatile memory having encrypted and integrity-protected code pages, an external volatile memory for swap pages and a processor coupled to said secure internal memory and to said external non-volatile memory and operable to decrypt and verify the integrity of the code pages thereby to transfer code pages to said secure internal memory directly from said external non-volatile memory bypassing said external volatile memory in respect of the code pages, and to swap out and swap in the swap pages between secure internal memory and said external volatile memory bypassing said external non-volatile memory in respect of the swap pages for said external volatile memory.

Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices

Systems and methods for providing a battery modulewith secure identity information and authentication of the identity of the batteryby a host. In one embodiment, the system for providing a battery module with secure identity information includes: (1) a tamper resistant processing environmentlocated within the battery moduleand (2) a key generator configured to generate a key based on an identity of the battery moduleand cause the key to be stored within the tamper resistant processing environment

Host/battery with public/private busses, public memory, processor, and private memory

Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making

Authentication with battery and host programmed with shared identity key

A secure demand paging system includes a secure internal memory having a table relating physical addresses to virtual addresses, a non-volatile memory, a decryption module and a hash module between the secure memory and the non-volatile memory to allow for decryption and integrity verification of data stored in the non-volatile memory during a transfer to said secure memory and means for connecting the secure memory to a volatile page swap memory such that the non-volatile memory is bypassable during a page swap.

A secure demand paging system includes a processor operable for executing instructions, an internal memory for a first page in a first virtual machine context, an external memory for a second page in a second virtual machine context, and a security circuit coupled to the processor and to the internal memory for maintaining the first page secure in the internal memory. The processor is operable to execute sets of instructions representing: a central controller, an abort handler coupled to supply to the central controller at least one signal representing a page fault by an instruction in the processor, a scavenger responsive to the central controller and operable to identify the first page as a page to free, a virtual machine context switcher responsive to the central controller to change from the first virtual machine context to the second virtual machine context; and a swapper manager operable to swap in the second page from the external memory with decryption and integrity check, to the internal memory in place of the first page.

An electronic circuitincludes a more-secure processor () having hardware based security () for storing data. A less-secure processor () eventually utilizes the data. By a data transfer request-response arrangement () between the more-secure processor () and the less-secure processor (), the more-secure processor () confers greater security of the data on the less-secure processor (). A manufacturing process makes a handheld device () having a storage space (), a less-secure processor () for executing modem software and a more-secure processor () having a protected application () and a secure storage (). A manufacturing process involves generating a per-device private key and public key pair, storing the private key in a secure storage () where it can be accessed by the protected application (), combining the public key with the modem software to produce a combined software, signing the combined software; and storing the signed combined software into the storage space (). Other processes of manufacture, processes of operation, circuits, devices, wireless and wireline communications products, wireless handsets and systems are disclosed and claimed.

Validating sensitive data from an application processor to modem processor

Public/private non-volatile memory battery with root key index, identity key

An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By a data transfer request-response arrangement between the more-secure processor and the less-secure processor, the more-secure processor confers greater security of the data on the less-secure processor. A manufacturing process makes a handheld device having a storage space, a less-secure processor for executing modem software and a more-secure processor having a protected application and a secure storage. A manufacturing process involves generating a per-device private key and public key pair, storing the private key in a secure storage where it can be accessed by the protected application, combining the public key with the modem software to produce a combined software, signing the combined software; and storing the signed combined software into the storage space. Other processes of manufacture, processes of operation, circuits, devices, wireless and wireline communications products, wireless handsets and systems are disclosed and claimed.

Wireless communications system communicating secyre SIM and IMEI between processors

A secure demand paging (SDP) system includes a dynamic random access memory (DRAM), a microprocessor having a secure internal memory and coupled to said DRAM, and a non-volatile memory storing a representation of operations accessible by the microprocessor. The stored representation of operations includes a coded physical representation of operations to configure an SDP space in the DRAM, to organize the SDP space into virtual machine contexts, to organize at least one of the virtual machine contexts into block book keeping blocks and book keeping spaces in the block book keeping blocks, and to execute a secure demand paging process between said secure internal memory and said DRAM.

Growing community of inventors

San Jose, CA, United States of America

Narendar M Shankar