Advanced Micro Devices Corporation

Adesto Technologies Corporation

Other

Fujitsu Corporation

Virage Logic Corporation

Agate Logic, Inc.

Adesto Technology Corporation

Agale Logic, Inc.

Spansion Llc.

Narbeh Derhacobian

Hao Fang

Ravi S Sunkavalli

Michael Allen Van Buskirk

Daniel Sobek

Darlene G Hamilton

Shane Charles Hollmer

Janet S Wang

Janet S Y Wang

Mark T Ramsbey

Chi K Chang

Pau-Ling Chen

Ishai Naveh

Hidehiko Shiraiwa

Jean Y Yang

David Michael Rogers

Kulachet Tanpairoj

Michael K Han

Timothy J Thurgate

Vei-Han Chan

Yider Wu

Antonietta Oliva

Louis Charles Kordus, Ii

Binh Quang Le

John Dinh

Nad Edward Gilbert

Masaaki Higashitani

Michael Van Buskirk

Jaroslav Raszka

Chung-You Hu

Joseph G Pawletko

K Michael Han

Kim-Kwong Michael Han

Angela Tai Hui

Sameer S Haddad

Tuan Duc Pham

Richard M Fastow

Mark W Randolph

Yue-Song He

Kent Kuohua Chang

Tim Thurgate

Colin Neal Murphy

Kelwin Ko

Ravi Sunkavalli

Janet Wang

Thomas E Stewart

Janet Sy Wang

Kulachet Kt Tanpairoj

Massaki Higashitani

Maria Chow-Chan

Bill Cox

A method can include, by operation of a controller circuit, writing data into a volatile memory portion formed in an integrated circuit substrate of a memory device. In response to first conditions, date can be written from the volatile memory portion into a nonvolatile memory portion formed in the same integrated circuit substrate as the volatile memory portion. The nonvolatile memory portion can store the data in two terminal memory elements re-programmable between at least two different resistance states.

Methods of operating integrated circuit devices having volatile and nonvolatile memory portions

A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element.

Read operations and circuits for memory devices having programmable elements, including programmable resistance elements

An integrated circuit may can include a memory section that stores data in programmable impedance elements arranged at cross points of select lines and sub bit lines, groups of sub bit lines each being connected to a different main bit line, the elements being formed above a substrate surface.

Programmable impedance element circuits and methods

An integrated circuit (IC) device can include a plurality of memory cells with programmable impedance elements. A circuit can be configured to read a data value stored by an element of a memory cell by application of at least one read voltage pulse and at least one relaxation voltage pulse across the terminals of the element; wherein the read voltage pulse has a same polarity as a voltage used to program the element, the relaxation voltage pulse has a different polarity than the read voltage pulse, and neither the read or relaxation voltage pulses program the element to a particular impedance state.

Application of relaxation voltage pulses to programmble impedance elements during read operations

A memory device can include a plurality of memory cells, each including a dynamic section configured to store data dynamically, and a programmable impedance section comprising at least one programmable element programmable between at least two different data states, the programmable impedance section configured to establish a data value stored by the dynamic section in response to a recall signal.

Memory cells, devices and method with dynamic storage elements and programmable impedance shadow elements

Integrated circuit (IC) devices are disclosed that include programmable impedance elements (elements) as data storage element. In some embodiments, IC devices can include latch circuit with one or more elements that establish a function of an associated circuit. In other embodiments, IC devices can include elements arranged in a cross-point array connected to control terminals of access devices. In still other embodiments, a memory device can include a programmable address decoder. Corresponding methods are also disclosed.

Circuits and methods having programmable impedance elements

A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element. In other embodiments, a memory device can include both standard and strong read operations, where strong read operations apply more energy to a selected memory element than a standard read operation.

Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active terminals, with control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals, allowing use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. Programming control can be placed outside of main signal path through the phase change device, reducing impact of associated capacitance and resistance of the device.

Multi-terminal phase change devices

An integrated circuit (IC) device may include a first portion having a plurality of volatile memory cells; and a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable more than once between different resistance values. A memory device may also include variable impedance elements accessible by access bipolar junction transistors (BJTs) having at least a portion formed by a semiconductor layer formed over a substrate. A memory device may also include a plurality of memory elements that each includes a dielectric layer formed between a first and second electrode, the dielectric layer including a solid electrolyte with a soluble metal having a mobility less than that of silver in a germanium disulfide.

Circuits having programmable impedance elements

An integrated circuit (IC) device can include a memory array having memory elements formed with a solid ion conductor, the memory array programmable to provide portions with different response types; and a logic section comprising logic circuits configured to perform logic functions, the logic section being coupled to the memory array to store and read data values therefrom. A memory device can also have a plurality of access ports, each configurable to access any of the different portions of the memory array. A memory device can further include a read circuit configured to read data values from the different portions according to the response type of each portion.

Integrated circuit devices and systems having programmable impedance elements with different response types

Methods and circuits for CAM cells using PMCs are disclosed herein. In one embodiment, a BCAM cell can include: (i) a first PMC coupled to a first access transistor and a bit node, where the first access transistor is coupled to a true bit line; (ii) a second PMC cell coupled to a second access transistor and the bit node, where the second access transistor is coupled to a complement bit line, and the first and second access transistors are controllable by a word line; (iii) a program enable transistor coupled to the bit node, and configured to couple a program control voltage to the bit node when enabled; and (iv) a match indication transistor configured to discharge a match line in response to states of the true and complement bit lines relative to the bit node.

PMC-based non-volatile CAM

A memory device may include a plurality of memory cells each having elements with at least one solid ion conductor programmable between at least two different impedance states for at least two different data retention times, the plurality of memory cells being dividable into a plurality of portions, each portion being separately configurable for one of the data retention times.

Reconfigurable memory arrays having programmable impedance elements and corresponding methods

An integrated circuit may include a plurality of sub bit line groups, each sub bit line group coupled to a different main bit line by a corresponding access device; and a plurality of programmable impedance elements arranged into element groups, each element group being coupled to a corresponding each sub bit line.

Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

Growing community of inventors

Belmont, CA, United States of America

Narbeh Derhacobian