Freescale Semiconductor,inc.

Other

Narayanan Kannan

Rohit Srivastava

Ankit Jain

Madhur Kashyap

Pramod Sharma

A system and method of clocking an integrated circuit (IC) includes determining operating characteristics of the IC. The IC has multiple domains and each domain receives a respective domain clock signal. A skew value is determined for each of the domain clock signals, where each skew value is associated with a respective domain of the IC. The domain clock signals are generated from a reference clock signal and each domain clock signal is skewed from the reference clock according to the respective skew value.

System and method for clocking integrated circuit

An electronic design automation (EDA) tool for inserting dummy tiles between interconnect lines of an integrated circuit design includes a memory for storing the integrated circuit design and a processor in communication with the memory. The processor identifies those interconnect lines that are at different voltage levels, have a length greater than a predefined threshold length and a spacing less than a predefined threshold spacing, and inserts blockage areas between such interconnect lines. The processor skips the blockage areas and adds dummy tiles only between those interconnect lines that do not meet predetermined criteria.

System for placing dummy tiles in metal layers of integrated circuit design

A method of estimating capacitive cell load of cells in an integrated circuit (IC) design uses first maximum capacitive load values Cin calculating risk of electromigration failure in cells of the IC design. Cis saved for a cell whose risk of electromigration failure is acceptable. For a failed cell, a revised maximum capacitive load value Cis reduced as the ratio of an actual current Irelative to the electromigration current limit Iin the weakest element of the cell. A revised actual current Iis obtained as a function of transition times with C. Cis saved for the cell if Iis less than I. Otherwise the steps of calculating Cand Iare re-iterated. Cis reduced relative to Cfor the first iteration and is further reduced relative to its previous value Cfor subsequent iterations.

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Delhi, India

Narayanan Kannan