Arm Limited

Narayana Sri Harsha Gade

Nitin Kumar Agarwal

Anup Gangwar

Honnahuggi Harinath Venkata Naga Ambica Prasad

Ravishankar Sreedharan

A computer-based method and system for synthesizing a Network-on-Chip (NoC) is provided. One method includes determining physical data, device data, bridge data, traffic data and domain data based on an input specification for the NoC; assigning a domain to each bridge port; partitioning each traffic flow into one of a plurality of bins based on the bridge port domain assignments and the domain crossing constraints; creating a virtual node at each bridge port endpoint; generating a candidate topology for each bin based on the physical data, the device data, the bridge data, the traffic data, the domain data and the virtual nodes, each candidate topology including bridge ports, a tree of routers, routes and connections; and generating a final topology by merging the candidate topologies.

Network-on-chip topology generation

The present disclosure provides computer-based methods and a system for synthesizing a NoC that advantageously generate balanced NoC topologies without end-to-end fairness or local credit-based arbitration, and improve NoC performance when destination device bridge ports support only one incoming physical link per channel. More particularly, a clock domain is assigned to certain routers that satisfies the minimum frequency for the router while reducing clock domain transitions to neighboring routers, and the traffic flows received by these routers are balanced based on the traffic flow packet rates.

Network-on-Chip topology generation

The present disclosure provides a computer-based method and system for synthesizing a NoC. Traffic data is determined or received, and a baseline topology is generated or received. For each router in the baseline topology, a number of edge virtual channel (EVC) combinations is determined, the transmittablility of the traffic classes are determined, and, when the traffic classes are not transmittable, the router is identified. A traffic class affinity graph (TCAG) is generated for each identified router. Traffic class combinations are generated for the identified routers based on the TCAGs and EVC combinations. The traffic classes of the identified routers are merged based on the traffic class combinations. A final EVC combination for each identified router is determined based on the merged traffic classes. A final topology is generated based, at least in part, on the merged traffic classes and the final EVC combinations for the identified routers.

The present disclosure provides a computer-based method and system for synthesizing a Network-on-Chip (NoC). Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow to create a plurality of VC assignments. A topology is generated, based on the physical data, the device data, the bridge data, the traffic data and the VC assignments, which includes bridge ports, routers and connections. Final locations for relocatable NoC elements (e.g., routers, etc.) are determined based on NoC element energy values for the relocatable NoC elements, and protocol-level pipelines may be inserted into the connections based on a timing parameter.

Network-on-chip element placement

The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. The HGC is modified based on bridge data and the traffic data to generate a modified HCG. A plurality of traffic graphs (TGs) are constructed based on the physical data, the bridge data, the traffic data and the modified HCG. A candidate topology is generated for each TG, which includes the bridge ports, routers and connections. The candidate topologies are merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.

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Bengaluru, India

Narayana Sri Harsha Gade