Intel Corporation

Hrl Laboratories, LLC

Gm Global Technology Operations LLC

Xlabs Holdings, LLC

Raytheon Company

University of Pittsburgh

Htl Laboratories, LLC

Narayan Srinivasa

Altug Koker

Feng Chen

Abhishek R Appu

Joydeep Ray

Dukhwan Kim

Farshad Akhbari

Nadathur Rajagopalan Satish

Balaji Vembu

Kamal Sinha

Nicolas C Galoppo Von Borries

Eriko Nurvitadhi

Prasoonkumar Surti

Tsung-Han Lin

Justin E Gottschlich

Linda L Hurd

Sara S Baghsorkhi

Rajkishore Barik

Xiaoming Chen

Ben J Ashbaugh

Anbang Yao

John Charles Weast

Tatiana Shpeisman

Ping Tak Tang

Michael S Strickland

Jose Cruz-Albrecht

Subramaniam M Maiyuran

Travis T Schluessler

Vasanth Ranganathan

Sanjeev S Jahagirdar

Karthik Vaidyanathan

Adam T Lake

John H Feit

Jeffery S Boles

Devan Burke

Wenyin Fu

Josh B Mastronarde

Mike B Macpherson

Yuri Owechko

Swarup S Medasani

Jeremy Bottleson

Elmoustapha Ould-Ahmed-Vall

Chandrasekaran Sakthivel

Peter Petre

Suhas E Chelian

Youngkwan Cho

Yongqiang Cao

Corey M Thibeault

Liwei Ma

Qin Jiang

Kevin Nealis

Arnab Paul

Leandro G Barajas

Deepak Khosla

Narayan Biswal

Stanley J Baran

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Archie Sharma

Mayuresh M Varerkar

Aleksey Nogin

Sherine Abdelhak

Riccardo Boscolo

Sachin B Godse

Rajan Bhattacharyya

Praveen K Pilly

Shankar R Rao

Barath Lakshmanan

David B Shu

Rashmi N Sundareswara

Michael W Yung

Kirill Minkovich

Timothy J Derosier

Nabil Imam

Vivek K De

Nasser A Kurd

Gautham N Chinya

Yilu Zhang

Mike MacPherson

Michael J Daily

Sriram R Vangal

David J Huber

Vincent De Sapio

Mohamed A Abdelmoneum

Nick S Kapsokavathis

Kevin R Martin

Shubha Kadambe

Justin Hogaboam

Craig A Lee

Krzysztof Wojtek Przytula

Peter Sagazio

Farzin Guilak

Donald M Chiarulli

Steven P Levitan

Karl Paul Dockendorf

Thripthi Hegde

Chit Kwan Lin

Deying Zhang

Miguel Bautista Gabriel

Apparatuses, methods, and articles of manufacture are disclosed. An example apparatus includes processor circuitry to assign a location value hyperdimensional vector (HDV) to a location in an image of a first patch of one or more pixels, assign at least a first channel HDV to the first patch, determine at least one pixel intensity value HDV for each of the one or more pixels in the first patch, bind together each of the pixel intensity value HDVs into at least one patch intensity value HDV, bind together the at least first channel HDV and the at least one patch intensity value HDV to produce a patch consensus intensity HDV, and generate a first hyperdimensional representation patch value HDV of the first patch by binding together at least a combination of the patch consensus intensity HDV and the location value HDV.

Apparatus, method, and computer-readable medium for robust response to adversarial perturbations using hyperdimensional vectors

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

An integrated circuit (IC) is provided for in-situ anomaly detection. Sensors in the IC generates sensor datasets including information indicating conditions in the IC. A processing unit in the IC uses a sensor dataset and a model to detect and classify the anomaly. The processing unit may filter the sensor dataset, extract features from the filtered sensor dataset, and input the features into the model. The model outputs one or more classifications of the anomaly. A feature may be a distance vector that represents a difference between a data value in the filtered sensor dataset from a reference data value. The model may be a network of bit-cells in the IC. The model may be continuously trained in-situ, i.e., on the IC. The processing unit may provide the classifications to another processing unit in the IC. The other processing unit may mitigate the anomaly based on the classifications.

In-situ detection of anomalies in integrated circuits using machine learning models

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

Compute optimization mechanism

A clock buffer or driver is gated pending reception of verifiable crypto keys. These clock buffer or divers remain gated, thus disabling a processor from any meaningful function, till crypto keys are decoded, verified, and applied to the clock buffer or driver. A low frequency pseudorandom frequency hopping time sequence is generated and used for randomizing spread-spectrum to modulate a reference clock (or output clock) of a frequency synthesizer. This hopping time sequence holds the key to unlocking the crypto keys. The PWM modulated crypto keys are carried by the hopping time sequence. To decode the PWM modulated crypto keys, the hopping time sequence is used. The reference clock which is modulated with crypto keys in the spread-spectrum is sent to a decoder (in a processor) along with the hopping time sequence. The crypto keys are decoded and then used to un-gate the clock buffer.

Intellectual property security locking apparatus and method

An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

Graphics processing integrated circuit package

One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex compute operation.

Techniques and mechanisms for providing a logical state machine with a spiking neural network which includes multiple sets of nodes. Each of the multiple sets of nodes is to implement a different respective state, and each of the multiple spike trains is provided to respective nodes of each of the multiple sets of nodes. A given state of the logical state machine is implemented by configuring respective activation modes of each node of the corresponding set of nodes. The activation mode of a given node enables that node to signal, responsive to its corresponding spike train, that a respective state transition of the logical state machine is to be performed. In another embodiment, the multiple spike trains each represent a different respective character in a system used by data evaluated with the spiking neural network.

Parsing regular expressions with spiking neural networks

Techniques and mechanisms for processing differential video data with a spiking neural network to provide action recognition functionality. In an embodiment, the spiking neural network is coupled to receive and process a first one or more spike trains which represent an encoded version of a sequence comprising frames of differential video data. In turn, the frames of differential video data are each based on a difference between a respective two frames of raw video data. Based on the processing of the first one or more spike trains, the spiking neural network may output a second one or more spike trains. In another embodiment, the second one or more spike trains are provided to train the spiked neural network to recognize an activity type, or to classify a video sequence as including a representation of an instance of the activity type.

Method, apparatus and system to perform action recognition with a spiking neural network

Growing community of inventors

Oak Park, CA, United States of America

Narayan Srinivasa