Symetrix Corporation

Other

Matsushita Electronics Corporation

Siemens Aktiengesellschaft

Matsushita Electric Industrial Co., Ltd.

Primaxx, Inc.

Sand Hill Capital Ii, LP

Narayan Solayappan

Carlos Alberto Paz De Araujo

Larry D McMillan

Vikram Joshi

Shinichiro Hayashi

Joseph D Cuchiaro

Jolanta Bozena Celinska

Kiyoshi Uchiyama

Gary F Derbenwick

Walter Hartner

Michael C Scott

Koji Arita

Robert W Grant

Gunther Schindler

Jeffrey W Bacon

Myoungho Lim

Tatsuo Otsuki

G&uuml;nther Schindler

Carlos Mazure

A three-dimensional ('3-D') memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm, and the corresponding capacitance area is typically in a range of from 0.4 nmto 1.0 nmThe ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.

Ferroelectric and high dielectric constant integrated circuit capacitors with three-dimensional orientation for high-density memories, and method of making the same

A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.

Stacked memory cell having diffusion barriers

A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450&#xb0; C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.

Barrier layers for protecting metal oxides from hydrogen degradation

A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of BiOwith an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas ABO, ABOand ABiBO, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaSr)(TaNb)O, where 0&#x2266;y&#x2266;1.0 and 0&#x2266;y&#x2266;1.0; (BaSr)(TaNb)O, where 0&#x2266;x&#x2266;1.0 and 0&#x2266;y&#x2266;1.0; and (BaSr)Bi(TaNb)O, where 0&#x2266;x&#x2266;1.0 and 0&#x2266;y&#x2266;1.0. Thin films according to the invention have a relative dielectric constant &#x2267;40, and preferably about 100. The value of Vcc in the metal oxides of the invention is close to zero. The value of Tcc is &#x3c;1000 ppm, preferably &#x3c;100.

Interlayer oxide containing thin films for high dielectric constant application of the formula AB2O6 or AB2O7

A ferroelectric memory ( ) includes a plurality of memory cells ( ) each containing a ferroelectric thin film ( ) including a microscopically composite material having a ferroelectric component ( ) and a dielectric component ( ), the dielectric component being a different chemical compound than the ferroelectric component. The dielectric component is preferably a fluxor, i.e., a material having a higher crystallization velocity than the ferroelectric component. The addition of the fluxor permits a ferroelectric thin film to be crystallized at a temperature of between 400&deg; C. and 550&deg; C.

Ferroelectric composite material, method of making same and memory utilizing same

A precursor for forming a thin film of layered superlattice material is applied to an integrated circuit substrate. The precursor coating is heated using rapid thermal processing (RTP) with a ramping rate of 100&deg; C./second at a hold temperature in a range of from 500&deg; C. to 900&deg; C. for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell, the coating is heated in oxygen using RTP, then a top electrode layer is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film of layered superlattice material preferably comprises strontium bismuth tantalate or strontium bismuth tantalum niobate, and preferably has a thickness in a range of from 25 nm to 120 nm. The process of fabricating a thin film of layered superlattice material typically has a thermal budget value not exceeding 960,000&deg; C.-sec, preferably less than 50,000&deg; C.-sec.

Low thermal budget fabrication of ferroelectric memory using RTP

A method of forming a Bi-layered superlattice material on a substrate using chemical vapor deposition of a precursor solution of trimethylbismuth and a metal compound dissolved in an organic solvent. The precursor solution is heated and vaporized prior to deposition of the precursor solution on an integrated circuit substrate by chemical vapor deposition. No heating steps including a temperature of 650&deg; C. or higher are used.

Chemical vapor deposition method of making layered superlattice materials using trimethylbismuth

A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450&deg; C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.

A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (&ldquo;RTP&rdquo;) and furnace annealing steps.

Chemical vapor deposition process for fabricating layered superlattice materials

A thin film of precursor for forming a layered superlattice material is applied to an integrated circuit substrate, then a strong oxidizing agent is applied at low temperature in a range of from 100&deg; C. to 300&deg; C. to the precursor thin film, thereby forming a metal oxide thin film. The strong oxidizing agent may be liquid or gaseous. An example of a liquid strong oxidizing agent is hydrogen peroxide. An example of a gaseous strong oxidizing agent is ozone. The metal oxide thin film is crystallized by annealing at elevated temperature in a range of from 500&deg; C. to 700&deg; C., preferably not exceeding 650&deg; C., for a time period in a range of from 30 minutes to two hours. Annealing is conducted in an oxygen-containing atmosphere, preferably including water vapor. Treatment by ultraviolet (UV) radiation may precede annealing. RTP in a range of from 500&deg; C. to 700&deg; C. may precede annealing.

Low temperature oxidizing method of making a layered superlattice material

An integrated circuit includes a layered superlattice material having the formula A A . . . Aj S S . . . Sk B B . . . Bl Q , where A , A . . . Aj represent A-site elements in a perovskite-like structure, S , S . . . Sk represent superlattice generator elements, B , B . . . B represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w and y are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.

Ferroelectric and high dielectric constant transistors

A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi O with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB O , A B O and A Bi B O , wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (Ba Sr )(Ta Nb ) O , where 0&lE;x&lE;1.0 and 0&lE;y&lE;1.0; (Ba Sr ) (Ta Nb ) O , where 0&lE;x&lE;1.0 and 0&lE;y&lE;1.0; and (Ba Sr ) Bi (Ta Nb ) O , where 0&lE;x&lE;1.0 and 0&lE;y&lE;1.0. Thin films according to the invention have a relative dielectric constant &gE;40, and preferably about 100. The value of Vcc in the metal oxides of the invention is close to zero. The value of Tcc is <1000 ppm, preferably <100.

Growing community of inventors

Colorado Springs, CO, United States of America

Narayan Solayappan