Intel Corporation

Narayan Ranganathan

Rajesh M Sankaran

Francesc Guim Bernat

Ashok Raj

Mohan J Kumar

Karthik Kumar

Thomas Willhalm

Robert Valentine

Gilbert A Neiger

Mark Jay Charney

Jesus Corbal

Edward Thomas Grochowski

Eriko Nurvitadhi

Raj K Ramanujan

Koichi Yamada

Thomas D Fletcher

Sanjay Kumar

Joseph Nuzman

Philip R Lantz

Deborah T Marr

Stephen R Van Doren

Paul Caprioli

Dennis Ryan Bradford

Lokpraveen B Mosur

Kent D Glossop

Jonathan D Pearce

Niall D McDonnell

Richard J Greco

Jeffrey J Cook

Ganesh Venkatesh

Asit K Mishra

Dwight P Manley

David B Sheffield

Tracy Garrett Drysdale

Nicholas P Carter

Saurabh Gayen

Michael A O'Hanlon

Robert G Blankenship

Robert Charles Swanson

Utkarsh Y Kakaiya

Sarathy Jayakumar

Dhananjay A Joshi

Sujoy Sen

Murugasamy K Nachimuthu

Rahul Khanna

Mahesh S Natu

Susanne M Balle

Ramamurthy Krithivas

Anil S Keshavamurthy

John C Leung

Nicolas A Salhuana

Nikhil P Rao

Vincent J Zimmer

Kshitij Arun Doshi

Ren Wang

Mark A Schmisseur

Mallik Bulusu

Jr-Shian Tsai

Pete D Vogt

David A Koufaty

Evan Custodio

Sameh Gobriel

Edwin Verplanke

Theodros Yigzaw

Sergiu D Ghetie

Rupin H Vakharwala

Sivakumar Radhakrishnan

Nilesh K Jain

Brinda Ganesh

Paul H Dormitzer

Yipeng Wang

Somnath Paul

John G Holm

Robert Bruce Bahnsen

David N Lombard

Charles A Giefer

Chet R Douglas

Donald L Faw

John Chun Kwok Leung

Mrittika Ganguli

Priya Autee

Sriram Kabisthalam Muthukumar

Abhirupa Layek

Abhijit Davare

Dan J Williams

Anton Alexandrovich Sorokin

Vishal Verma

Desmond A Kirkpatrick

Suvadeep Banerjee

David Jiang

Shaman Narayana

Jaykant B Timbadiya

Nalini Murari

Niall D Mcdonnell

Michael A O'HANLON

Methods and apparatus relating to scalable access control checking for cross-address-space data movement are described. In an embodiment, a memory stores an Inter-Domain Permissions Table (IDPT) having a plurality of entries. At least one entry of the IDPT provides a relationship between a target address space identifier and a plurality of requester address space identifiers. A hardware accelerator device allows access to a target address space, corresponding to the target address space identifier, by one or more of requesters, corresponding to the plurality of requester address space identifiers, respectively, based at least in part on the relationship provided by the at least one entry of the IDPT. Other embodiments are also disclosed and claimed.

Scalable access control checking for cross-address-space data movement

Apparatus and method for high-performance page fault handling. For example, one embodiment of an apparatus comprises: one or more accelerator engines to process work descriptors submitted by clients to a plurality of work queues; fault processing hardware logic associated with the one or more accelerator engines, the fault processing hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, the page fault handling modes including a first page fault handling mode and a second page fault handling mode.

Method and apparatus for high-performance page-fault handling for multi-tenant scalable accelerators

Techniques for offload device address translation fetching are disclosed. In the illustrative embodiment, a processor of a compute device sends a translation fetch descriptor to an offload device before sending a corresponding work descriptor to the offload device. The offload device can request translations for virtual memory address and cache the corresponding physical addresses for later use. While the offload device is fetching virtual address translations, the compute device can perform other tasks before sending the corresponding work descriptor, including operations that modify the contents of the memory addresses whose translation are being cached. Even if the offload device does not cache the translations, the fetching can warm up the cache in a translation lookaside buffer. Such an approach can reduce the latency overhead that the offload device may otherwise incur in sending memory address translation requests that would be required to execute the work descriptor.

Technologies for offload device fetching of address translations

Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

Hardware offload circuitry

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

In one embodiment, a data mover accelerator is to receive, from a first agent having a first address space and a first process address space identifier (PASID) to identify the first address space, a first job descriptor comprising a second PASID selector to specify a second PASID to identify a second address space. In response to the first job descriptor, the data mover accelerator is to securely access the first address space and the second address space. Other embodiments are described and claimed.

System, apparatus and method for accessing multiple address spaces via a data mover

In one embodiment, an apparatus comprises a fabric controller of a first computing node. The fabric controller is to receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric.

Method and apparatus for remote field programmable gate array processing

Technologies for accessing pooled accelerator resources over a network fabric are disclosed. In disclosed embodiments, an application hosted by a computing platform accesses remote accelerator resources over a network fabric using protocol multipathing mechanisms. A communication session is established with the remote accelerator resources. The communication session comprises at least two connections. The at least two connections at least include a first connection having or utilizing a first transport layer and a second connection having or utilizing a second transport layer that is different than the first transport layer. Other embodiments may be disclosed and/or claimed.

Technologies for accelerator fabric protocol multipathing

Technologies for pooling accelerators over fabric are disclosed. In the illustrative embodiment, an application may access an accelerator device over an application programming interface (API) and the API can access an accelerator device that is either local or a remote accelerator device that is located on a remote accelerator sled over a network fabric. The API may employ a send queue and a receive queue to send and receive command capsules to and from the accelerator sled.

Technologies for pooling accelerator over fabric

A host fabric interface (HFI) apparatus, including: an HFI to communicatively couple to a fabric; and a remote hardware acceleration (RHA) engine to: query an orchestrator via the fabric to identify a remote resource having an accelerator; and send a remote accelerator request to the remote resource via the fabric.

Remote hardware acceleration

Systems, methods and apparatuses for distributed consistency memory. In some embodiments, the apparatus comprises at least one monitoring circuit to monitor for memory accesses to an address space; at least one a monitoring table to store an identifier of the address space; and at least one hardware core to execute an instruction to enable the monitoring circuit.

Systems, methods, and apparatuses for distributed consistency memory

Growing community of inventors

Bengaluru, India

Narayan Ranganathan