Toshiba Memory Corporation

Kioxia Corporation

Lsi Logic Corporation

Lsi Corporation

Narasimhulu Dharani Kotte

Senthil Thangaraj

Steven E Wells

Amit Jain

Girish Desai

Robert Reed

Mark Carlson

Barada Mishra

Senthil Thamgaraj

Hitoshi Kondo

Paresh Chatterjee

Basavaraj Gurupadappa Hallyal

Ragendra Mishra

Ramya Subramanian

In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the first region in the first operation mode.

SSD architecture supporting low latency operation

A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area. In one embodiment, the pSLC cache comprises a first area for a pSLC write cache and a second area for a pSLC read cache.

Multibit NAND media using pseudo-SLC caching technique

A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. The SSD further includes one or more volatile memory devices communicatively coupled to the memory controller, where at least one of the one or more volatile memory devices has a read cache area. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC write cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area.

The present invention provides a method for transmitting a non-SCSI command via a SCSI command. A CDB for the SCSI command is provided. The CDB includes bytes byte, byte, byte, . . . , byte_n, in which byteincludes an opcode for the SCSI command. An opcode for the non-SCSI command is loaded into byte. When the non-SCSI command is not greater than a fixed number of bytes, the non-SCSI command is loaded into at least one byte of the CDB, which includes byte. Data associated with the non-SCSI command is transmitted via a data phase associated with the SCSI command.

Methods of transmitting non-SCSI commands involving loading opcode in command descriptor block (CDB) bytes and non-SCSI commands into remaining CDB bytes

A mechanism is provided for migration between stripe storage and redundant parity striped storage. When a disk is added to a disk array, the mechanism migrates from RAID 0 to RAID 5. For each row, the mechanism calculates parity for the row and, if the parity position is not the new drive, the mechanism writes the data from the parity position to the new drive and writes the parity to the parity stripe position. If a drive fails, the mechanism migrates back from RAID 5 to RAID 0. For each row, if the parity position is not the failed drive, reads the data from remaining drives, XORs the data stripes to get failed drive data, and writes the failed drive data to the parity position. If a read or write is received for the failed drive, the mechanism simply redirects the read or write to the parity position.

Method, apparatus and program for migrating between striped storage and parity striped storage

Growing community of inventors

Fremont, CA, United States of America

Narasimhulu Dharani Kotte