Redpine Signals, Inc.

Radpine Signals, Inc.

Narasimhan Venkatesh

Satya Rao

Sankabathula Dharani Naga Sailaja

Venkat Mattela

Heonchul Park

Ponnamanda Venkata Chandra Sekhar

Dhiraj Sogani

Satyanarayana Rao

Venkata Rao Gunturu

Apurva Peri

Parthasarathy Murali

Ravikumar Neerudu

Partha Sarathy Murali

Dharani Naga Sailaja Sankabathula

Kovuri Sridhar

Murali Partha Sarathy

A product synthesizer has a core CPU, power distribution, and a plurality of selectable interfaces, each interface having an associated schematic symbol, PCB symbol, mechanical model, power dissipation, and power requirement. A set of constraints identifies performance metrics including low power, high performance, battery or mains power, battery life, and other constraints. The product synthesizer receives as inputs the interfaces and constraints, and generates as outputs a schematic diagram, a bill of materials, a routed printed circuit board, and a solid model of an enclosure, all of which satisfy the constraints and include the identified interfaces.

IoT product synthesis apparatus and method

A wireless LAN station having a MAC address and receiving beacon frames indicating a beacon interval selects a sub-interval from the beacon interval for transmission and reception of wireless signals. The beacon sub-interval used by each set of stations for transmission and reception is preferably &#xbd;of the beacon interval, where n is the number of device-unique assignment bits, such as MAC address. Each station thereby self-assigns itself one of the sub-intervals as a segment for transmission and reception, thereby reducing collisions and re-transmissions in a congested access point.

Automatic time slicing of beacon intervals in high density wireless LAN

A station or access point has a list of associated stations including a BSSID. During an observation period, measurements of RSSI are made for each BSSID, including a maximum RSSI and a minimum RSSI. After the observation interval, an RSSI_threshold is computed which is below the weakest RSSI of a station which is on the list of associated stations, and also above the weakest RSSI of a station which is not on the list of associated stations. During packet reception, packet acquisition starts when the receiver signal level is detected to be above the RSSI_threshold. During packet transmission, a clear channel assessment (CCA), which ordinarily prevents transmission when signal energy is detected, is overridden if the measured RSSI is below the RSSI_threshold value, enabling earlier transmission of the packet than if the transmitter were to wait for CCA to be asserted.

Received signal strength indication for use as a baseband processor qualifier in high density WLAN environments

A channel access processor for an access point operates in a frequency spectrum which is divided into master channels, each master channel further having a plurality of sub-channels, each sub-channel capable of supporting wireless LAN communications independently from any other said sub-channel of the master channel. Each master channel is thereby associated with a plurality of sub-channels, and the sub-channels each have an associated bandpass filter and mixer frequency specific to that sub-channel, thereby allowing a plurality of independent wireless communications sessions to simultaneously take place over the multiple sub-channels of the master channel of the access point.

Access point processor for a wireless local area network utilizing multiple sub-channels

A wireless signal processor for handling a plurality of wireless sessions comprises a plurality of baseband receivers, one for each session, each receiver producing a digital output, a multiplexer for multiplexing the plurality of digital outputs into a single data stream, a digital signal processor for converting the stream of multiplexed data into a media access controller format, and a media access controller for demultiplexing and framing the stream of data into a plurality of data buffers, one data buffer for each wireless session.

Multi-thread media access controller with per-thread MAC address

A reduced complexity maximum likelihood decoder receives a stream of received symbols Y accompanied by a channel estimate matrix H. A variable transformation part includes a first part which converts Y and H into Z and R by computing a matrix R having at least one non-zero element in a row, such that the product of R and Q produces matrix H. A second variable transformation part column-swaps matrix H to form H', thereafter generating Q&#x2032; and R&#x2032; subject to the same constraints as was described for Q and R. Transformed variables Z and Z&#x2032; are formed by multiplying Y by Qand Q&#x2032;, respectively. A reduced complexity maximum likelihood decoder has a first part which accepts Z and R and forms a first metric table having entries of all possible x2 accompanied by estimates of xderived from xand Z, and also including a distance metric. The reduced complexity maximum likelihood decoder has a second part which accepts Z&#x2032; and R&#x2032; and forms a second metric table having entries of all possible xaccompanied by estimates of xderived from xand Z&#x2032;, and also including a distance metric. A hard decision is made by finding the minimum distance metric of the combined entries of the first and second table. Soft values are also computed using this table.

Packet buffer management apparatus and method

A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with the pointers to be applied to a media access controller, which optionally contains an encryption function, the output of which is coupled to a block buffer and to an output interface. Upon receipt of a transmission request, the host memory locations associated with the pointers are read and the data directed to the media access controller, which adds a header, a CRC, and optionally encrypts the data, thereafter placing it in the block buffer and the output interface. Upon provision of the packet data to the MAC, the associated pointer is initialized to a FREE or UNUSED value, and upon receipt of an acknowledgement of the packet accompanied by a packet identifier from a receiving station, the packet associated with the packet identifier is removed from the block buffer.

Packet Re-transmission controller for block acknowledgement in a communications system

A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with said pointers to be applied to a media access controller, which optionally contains an encryption function, the output of which is coupled to a block buffer and to an output interface. Upon receipt of a transmission request, the host memory locations associated with the pointers are read and the data directed to the media access controller, which adds a header, a CRC, and optionally encrypts the data, thereafter placing it in the block buffer and the output interface. Upon provision of the packet data to the MAC, the associated pointer is initialized to a FREE or UNUSED value, and upon receipt of an acknowledgement of the packet accompanied by a packet identifier from a receiving station, the packet associated with the packet identifier is removed from the block buffer.

Packet re-transmission controller for block acknowledgement in a communications system

An interrupt controller for a dual thread processor has for a first thread, an interrupt request register accessible to the second thread, an interrupt count accessible to the second thread, and an interrupt acknowledge accessible to the first thread. Additionally, the interrupt controller has, for a second thread, an interrupt request register accessible to the first thread, an interrupt count accessible to the first thread, and an interrupt acknowledge accessible to the second thread. Each interrupt controller separately has a counter for each request which increments upon assertion of a request and decrements upon assertion of an acknowledgement.

Cross-thread interrupt controller for a multi-thread processor

A maximum likelihood CCK detector has a first subtractor which subtracts the contents of a pre-equalize register from a current symbol, and the output of this subtractor is coupled to a simple Fast Walsh Transform (FWT) with an iteration variable k. The output of the FWT is coupled to a second subtractor for subtracting a plurality of ICI corrections for all possible current symbols computed from the post-FWT domain value of the current CCK symbol and stored in post equalization registers. A post equalization register contains values computed from feedback filter coefficients determined during a packet preamble, where the feedback filter coefficients are provided to a reduced complexity post equalization value generator which populates the post equalization register using an iteration variable i.

Maximum likelihood block decision feedback estimation for CCK demodulation apparatus and method

A wireless link simulator includes, in sequence, a digital transmit device under test (TX-DUT), a wireless link simulator, and a digital receive device under test (RX-DUT). The wireless link simulator includes, in sequence, a transmitter IQ imbalance generator, a power amplifier non-linearity generator, a noise floor generator, a multi-path channel generator, a receive noise generator, a frequency offset generator, a phase noise generator, a receive IQ imbalance generator, and a DC offset generator. Each of the generators may be individually varied to determine the receiver sensitivity to each of these effects and associated parameters.

Wireless link simulator

A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system removes packets including a packet header and packet data from a packet buffer. The packet buffer is arranged into a plurality of packet buffer memory slots, each slot comprising a descriptor status array location including an availability bit set to 'used' or 'free', and a packet buffer memory location comprising a descriptor memory slot and a data segment memory slot. The descriptor memory slot includes header information for each packet, and the data segment memory slot includes packet data. The memory controller operates on one or more queues of data, and data is placed into a particular queue in packet memory determined by priority information derived from incoming packet header or packet data. Data is removed from packet memory based on which queue the data may be found in. The queues are based on a priority system, where one queue receives priority over another queue for data reception and transmission.

A baseband receiver having quadrature analog outputs and a plurality of analog control and status signals and a transmit modulator having analog quadrature inputs and a plurality of analog control and status signals are coupled to a transmit processor having a digital output and a plurality of digital control and status signals and to a receive processor having a digital input and a plurality of digital control and status signals by multiplexing analog to digital converters and digital to analog converters such that during a receive time the converters are used for a receive purpose and during a transmit time, the converters are used for a transmit purpose.

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Hyderabad Telangana, India

Narasimhan Venkatesh