International Business Machines Corporation

Narasimha R Adiga

Ashutosh Misra

Matthias D Heizmann

Akash V Giri

Jatin Bhartia

Anthony Saporito

James J Bonanno

Peter H Hochschild

Madhusudan Kadiyala

Manoj Dusanapudi

Embodiments of the invention are directed to a computer-implemented method of unit environment verification. The method includes monitoring, by a processor, a data stream between a first driver and a device under test (DUT) in a unit verification environment. The processor retrieves a transaction value from a database, wherein the transaction value was generated in a higher-level verification environment than the unit verification environment. The processor transmits the retrieved transaction value to the DUT. The processor compares a response from the DUT to the transmitted transaction value to an expected value. In response to the comparison indicating an error, the processor initiates a repair of the error at the unit verification environment.

Feedback from higher-level verification to improve unit verification effectiveness

Test case generation for a hardware state space including: identifying, from a first test case comprising a first plurality of test operations executed by a processor comprising a first configuration, a test operation causing an invalid result; determining a functional path associated with the test operation; generating a second plurality of test operations based on the functional path; generating a processor state by executing, by the processor comprising a second configuration, a subset of the first plurality of test operations comprising the determined test operation; and generate a second test case comprising the second plurality of test operations configured for execution based on the processor state.

Test case generation for a hardware state space

A method comprises identifying a number of branches (N) and a number of iterations (N) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals N, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than N&#x2212;1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than N, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.

Pattern based branch prediction

Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of 'n' divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of 'n' divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.

Testing optimization of microprocessor table functions

Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.

Variable updates of branch prediction states

Methods and structures that implement an event counter in a RAM are provided. A method includes providing a count-RAM, a carry-RAM, and a pre-counter corresponding to an event source. A column in the count-RAM and a column in the carry-RAM represent a value of a value of the event counter. The method further includes storing a count of the event counter received via the pre-counter in the count-RAM and the carry-RAM in a transposed, bit-serial format, such that location zero of the count-RAM and the carry-RAM counts the least significant bit (LSB) of the event counter.

RAM-based event counters using transposition

A method and arrangement for the implementation of a simple algorithm to store an N-bit checksum into any unaligned position within a larger NxP-bit word, which avoids the use of a logic-intensive implementation that employs a bank of demultiplexers, or a latency-increasing approach of 'read-modify-write'.

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Karnataka, India

Narasimha R Adiga