Intel Corporation

Narasimha Lanka

Debendra Das Sharma

Kuljit Singh Bains

Mahesh U Wagh

Nasser A Kurd

Swadesh Choudhary

Zuoguo Wu

Lakshmipriya Seshan

Gerald S Pasdast

Mahesh S Natu

Mohammad Mamunur Rashid

Michael C Rifani

Gregory M Iovino

Monib Ahmed

Eric Fetzer

Roman Rechter

Sridhar Muthrasanallur

Lohit Yerva

Grant Mcfarland

Pauline Goitia

Qinxin Yu

Kurt Heninger

Preethi Ramaswamy

Kit Seong Wong

Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.

Valid signal for latency sensitive die-to-die (D2D) interconnects

In one embodiment, an apparatus includes: a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry, after a reset flow for the first die, is to: perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die; and after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and thereafter perform a mainband training of the mainband interface at a negotiated data rate. Other embodiments are described and claimed.

Link initialization training and bring up for die-to-die interconnect

Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.

Clock-gating in die-to-die (D2D) interconnects

A port is to couple to another die over a die-to-die (D2D) link and includes a die-to-die (D2D) adapter to determine, from a set of registers, a set of capabilities of the D2D adapter to advertise in a negotiation with a link partner D2D adapter, where the D2D adapter is on a die and the link partner D2D adapter is located on a remote link partner die. A first capabilities advertisement message is sent to the link partner D2D adapter to advertise the set of capabilities to the link partner D2D adapter. A second capabilities advertisement message is received from the link partner D2D adapter, wherein the second capabilities advertisement message identifies a set of capabilities of the link partner D2D adapter. A final configuration of a D2D link is determined to couple the die to the link partner die.

Parameter exchange for a die-to-die interconnect

In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

Compliance and debug testing of a die-to-die interconnect

A multi-chip device having a configurable physical interface in a logic die to on-package memory is provided. The configurable physical interface to allow a connection from a signal on the memory interface to be selected based on whether the logic die is mirrored or non-mirrored.

Logic die in a multi-chip package having a configurable physical interface to on-package memory

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Dublin, CA, United States of America

Narasimha Lanka