Sharp Kabushiki Kaisha Corporation

Sharp Kabushiki Kaihsa

Narakazu Shimomura

Taku Fujii

Masahiro Hasegawa

Hitoshi Aoki

Mutsumi Hamaguchi

Toshio Mimoto

Kei Urakawa

Shinji Amano

Tadahiko Sato

Yan Qian

Shohji Sakurai

Koichi Kamiyama

Hiroyuki Teraoka

Eiji Nakaue

An in-vivo camera device and an in-vivo monitoring camera system more excellent in usability are proposed. An in-vivo camera device includes a camera unit introduced into a body, a support member, and a camera-side cable. The support member has a trocar connection portion for connection with a trocar at a front end side, and is connected to the trocar in a state in which the trocar connection portion is fitted into the trocar by applying tensile force to the camera-side cable passing through the trocar. The support member is provided with a guide introduction portion that is formed to be relatively long at the front end side as a stabilization structure for stabilizing connection with the trocar.

In-vivo camera device and in-vivo monitoring camera system

The present invention provides a touch panel controller for controlling even a large touch panel with little EMI. The touch panel controller of the present invention includes a plurality of driving circuits (DCthrough DCm) for driving respective drive lines (DLthrough DLm) of a capacitive touch panel unitby supplying driving signals (Ds) to the respective drive lines (DLthrough DLm), and a rise/fall time of each of the driving signals (Ds) is variable.

Touch panel controller, touch panel device, and electronic information device

In one embodiment of the present invention, an electrostatic discharge withstand voltage evaluating device includes: an application device, including a first connecting section and a second connecting section, for supplying pulse electric charge, the first connecting section being connectable to one or whole terminal (s) of one of input terminals and output terminals of a source driver, and supplying electric charge to the source driver, the second connecting section being connectable to one or whole terminal(s) of the other one of the input terminals and the output terminals, and enabling said one or whole terminal(s) of the other one of the input terminals and the output terminals to be grounded; and a common connecting section being connectable to the plurality of output terminals of the source driver, and causing the plurality of output terminals to be electrically connected to each other, wherein the output terminals of the source driver are connected, via the common connecting section, to one of the first connecting section and the second connecting section. Therefore, the electrostatic discharge withstand voltage evaluating device can more successfully recreate how a failure occurs in a semiconductor device and can evaluate an electrostatic discharge breakdown withstand of the semiconductor device.

Electrostatic discharge withstand voltage evaluating device and electrostatic discharge withstand voltage evaluating method

A semiconductor device has a semiconductor substrate of a first conductivity; and a first electrode formation region and a second electrode formation region formed adjacent to an inner surface of the semiconductor substrate. The first electrode formation regions and the second electrode formation regions are isolated from each other via an element isolation region. An upper first-type impurity layer and a lower first-type impurity layer are formed in one of the first electrode formation region and the second electrode formation region, the lower first-type impurity layer has a different first-type impurity concentration from the upper first-type impurity layer and is formed under the upper first-type impurity layer. A second-type impurity layer and a first-type impurity layer are formed in the other electrode formation region and the first-type impurity layer is formed under a part of the second-type impurity layer having second-type impurities.

Semiconductor device and manufacturing method thereof

A semiconductor device comprising an electrostatic protective element of the semiconductor device including a first conductivity type substrate and a second conductivity type high concentration diffusion layer formed on a surface of the substrate, and a semiconductor element including a source/drain and a gate electrode, wherein a first conductivity type diffusion layer having a higher concentration than the first conductivity type substrate is provided in an entire region under the second conductivity type high concentration diffusion layer.

Semiconductor device and method of manufacturing the same

An internal power voltage generating circuit of a semiconductor device includes a voltage dividing circuit composed of a single field effect transistor and a plurality of resistances incorporated into a semiconductor chip. The voltage dividing circuit divides an externally supplied power voltage into two types of voltage by conducting or non-conducting the single field effect transistor. The divided voltages are supplied as an internal power voltage to a plurality of field effect transistors incorporated into the semiconductor chip.

Internal power voltage generating circuit of semiconductor device

A semiconductor device comprising: a first wiring layer formed on a semiconductor substrate with an insulation film interposed therebetween, an interlayer insulation film and a second wiring layer formed on the first wiring layer in this order, wherein the interlayer insulation film is composed, from a first wiring layer side, of a first silicon oxide film having a compressive stress within the film, a silicon nitride film having a compressive stress within the film, a second silicon oxide film having a tensile stress within the film, and a third silicon oxide film having a compressive stress within the film.

Semiconductor device and method for manufacturing the same

A process of manufacturing a semiconductor device comprising: a step of forming an interlayer insulating film so as to cover a plurality of semiconductor elements formed on a semiconductor substrate, a step of forming openings in predetermined regions of the interlayer insulating film on the semiconductor elements in a manner of penetrating only halfway through the interlayer insulating film, a dual damascene step of forming contact hole by removing the interlayer insulating film remaining under the predetermined ones of the openings, thereby forming simultaneously openings for burying a wiring layer which include upper portions of the predetermined openings, a step of forming a conductive layer on the interlayer insulating film to fill at least the contact holes and the openings for burying the wiring layer; and a step of forming contact plugs and a buried wiring layer by removing the conductive layer on the interlayer insulating film.

Process of manufacturing semiconductor device

A method for manufacturing a semiconductor device including steps of (i) laminating a first insulating film over a semiconductor substrate having a plurality of gate electrodes, on which side walls are at least formed, through capacitor formation regions, removing the first insulating film in the capacitor formation region so as to form a direct contact, and laminating a first conductive film over the semiconductor substrate including the residual first insulating film, (ii) removing the first conductive film with remaining at least in the capacitor formation region, (iii) sequentially laminating over the semiconductor substrate including the residual first conductive film (a) a second insulating film, a second conductive film and a third insulating film, or (b) a second insulating film and a second conductive film, and then laminating a resist layer over the whole surface, and (iv) patterning the resist layer and removing with the use of a resist pattern (a) the third insulating film, second conductive film, second insulating film and first conductive film, or (b) the second conductive film, second insulating film and first conductive film, so that the capacitor electrodes of a FEC type DRAM cell including a capacitor upper electrode, a capacitor insulating film and a capacitor lower electrode can be formed in the capacitor formation region.

Method for manufacturing a semiconductor device

A method of manufacturing a semiconductor memory includes the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer simply except a portion where a contact hole is to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and a pattern film for forming the contact hole over the entire surface again; and v) removing the insulating film, the remaining conductive layer and the layer insulating film by etching one after another to form the contact hole extending to the diffused region in self-alignment, and forming a toothed projection of the insulating film which remains after the etching at an upper opening of the contact hole by removing the pattern employed for forming the contact hole.

Method of manufacturing a semiconductor memory

A method of manufacturing a semiconductor memory includes the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer simply except a portion where a contact hole is to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and a pattern film for forming the contact hole over the entire surface again; and v) removing the insulating film, the remaining conductive layer and the layer insulating film by etching one after another to form the contact hole extending to the diffused region in self-alignment.

Growing community of inventors

Gojo, Japan

Narakazu Shimomura