Fujitsu Corporation

Naozumi Aoki

Masaki Ukai

Aiichiro Inoue

Go Sugizaki

Yuji Kondo

Hideyuki Unno

Tsuyoshi Motokurumada

Miyuki Ishida

Masatoshi Sugino

Yukihiko Kitano

Isao Azuma

Kenro Nagato

An arithmetic processor includes a memory access controller configured to control access of a memory based on a memory access request. The memory access controller includes a shift register configured to shift a resource number and a memory access request from a first stage to a subsequent stage of the first stage at a timing according to the operation mode, the first stage is received a resource number and a memory access request. The memory access controller includes a plurality of memory access transmitting circuits configured to receive the resource number and the memory access request held by the plurality of stage. Each of the plurality of access transmitting circuits provided corresponding to the plurality of resource number, and output, to the memory, an access command corresponding to the memory access request when the received resource number matches a resource number of a memory access transmitting circuit.

Arithmetic processor and arithmetic apparatus

An information processing apparatus, a memory control method, and a memory control device are disclosed, the information processing apparatus including nodes each having a main memory, a processor including a cache memory, and a system controller. The system controller of at least one of the nodes includes a holding unit that holds address information corresponding to primary data stored in the main memory of its local node, and not cached in any of the cache memories of other nodes. The system controller of the at least one node may include local and global snoop control units, as well as a virtual tag expansion (VTAGx) unit, to maintain cache coherency, and under certain conditions, a snoop operation may be skipped or omitted.

Information processing apparatus, memory control method, and memory control device utilizing local and global snoop control units to maintain cache coherency

A transmitting side device () and a receiving side device () are connected to each other via a bus () comprising TAG bits (), data bits () and error detection/correction ECC bits (). The transmitting side device () uses a redundant bit inversion circuit () to invert different bits of the ECC bits () corresponding to trigger signals (&). In the receiving side device (), a determination circuit (), which has received an error report signal () from an error detection/correction circuit (), determines, from the position of an error bit in the ECC bits (), which one of the trigger signals (&) has been transmitted from the transmitting side device ().

Control method of information processing device and information processing device

A memory control method and a memory control device each suitable for information processing systems such as multiprocessing systems where plural data processing systems concurrently execute an operating process, and more particularly a memory control method and a memory control device each of which controls the data holding state of a buffer memory unit arranged in each of data processing units on a store-in basis to gain high speed access to the main storage unit. The memory control device issues a predetermined process command to be sent to the buffer memory unit in the data processing unit, and sets a flag showing a process under request, to a portion to be processed by the predetermined process command in a tag copying unit in the memory control device. Information regarding whether a block including a process request address exists in the buffer memory unit and whether the block is being processed currently are simultaneously obtained by retrieving only the tag copying unit. Thus, the address comparing unit can be omitted because no address comparison is needed. This structure reduces the amount of hardware and improves the port use efficiency, thus realizing the reduced system construction cost and improved processing speed.

Memory control method/device for maintaining cache consistency with

An electronic circuit device able to diagnose a status-holding circuit by scanning, the device comprising a first plurality of integrated circuits each including a serial scan circuit for receiving serial data, generating an address value of a target status-holding circuit as parallel data from the received serial data, and selecting the target status-holding circuit having the generated address value, and a second plurality of integrated circuits each including a parallel scan circuit for receiving an address value of a target status-holding circuit as parallel data and selecting the target status-holding circuit having the received address value. Address information received as serial data being used for generating parallel address information, and address information received as parallel data being used for generating serial address information.

Growing community of inventors

Kawasaki, Japan

Naozumi Aoki