Kabushiki Kaisha Toshiba

Ricoh Company, Ltd.

Naoyuki Tamura

Takeshi Yoshida

Takayuki Kamei

Yukihiro Urakawa

Hiroki Yoshida

Takuya Fukuhara

Naoka Yano

Tsubasa Hashimoto

You Yamamoto

A binding apparatus to bind sheets includes a binding device, a non-volatile memory, and control circuitry. The binding device is configured to bind a plurality of stacked sheets with a binding member. The non-volatile memory is configured to store a quantity of binding members in the binding device. The control circuitry is configured to control operation of the binding device. The control circuitry outputs an alert when the quantity of binding members stored in the non-volatile memory is equal to or less than a first predetermined value and cancels the alert when the quantity of binding members is equal to or less than a second predetermined value.

Binding apparatus and image forming system including the same

A sheet processing apparatus includes an overlap conveying unit that conveys two or more sheets in an overlapping manner; a stacking unit that stacks therein the sheets conveyed in the overlapping manner; an aligning unit that includes a rotating body and a regulating member and is configured to bring the rotating body into contact with a topmost sheet among the stacked sheets, so as to make the sheet abut the regulating member and align ends of the sheets; and a controller that controls the overlap conveying unit. The controller is configured to determine, according to sheet information, whether to make the topmost sheet overlap in a condition of projecting from the other sheets.

Sheet processing apparatus and image forming system

A method for manufacturing a semiconductor integrated circuit uses layout data designed by a sequence of processes. The sequence of processes includes disposing a lower-layer wiring pattern on an imaginary lower-layer wiring layer and an upper-layer wiring pattern perpendicular to the lower-layer wiring pattern on an imaginary upper-layer wiring layer implemented in the graphics image space, providing a detour pattern including a first detour pattern connected to the upper-layer wiring pattern, providing a plurality of via patterns connecting the lower-layer and upper-layer wiring patterns, and forming a via cell pattern.

Method of manufacturing a semiconductor integrated circuit, a program for a computer automated design system, and a semiconductor integrated circuit

A method including receiving, for respective terminals, wiring enable/disable information which sets a region where a connection of a wiring line is enabled and a region where a connection of a wiring line is disabled, and storing the wiring enable/disable information, and determining, using the wiring enable/disable information, whether a connection of a wiring line to a predetermined portion of a terminal of an element is enabled, and when the connection of the wiring line is enabled, executing the connection, wherein the wiring enable/disable information sets wiring enable regions at two end portions of the terminal, sets a wiring disable region at a central portion of the terminal except the two end portions, and sets an interval between either end face of the terminal and another wiring line different in longitudinal direction from the terminal to a predetermined interval not smaller than a minimum interval defined by a design rule.

Semiconductor integrated circuit routing method and recording medium which stores routing software

According to the present invention, there is provided a semiconductor integrated circuit layout design method of laying out standard cells by using a layout apparatus including an input unit, an arithmetic unit, and a storage unit, comprising, causing the arithmetic unit to calculate an area necessary for layout of each standard cell by using data about a plurality of kinds of standard cells having different heights in a row direction, which is stored in the storage unit in advance, causing the arithmetic unit to calculate the numbers of stages of row regions having heights corresponding to the standard cells on the basis of the calculated area, and causing the arithmetic unit to lay out the standard cells in the corresponding row regions.

Semiconductor integrated circuit including standard cell, standard cell layout design method, and layout design software product stored in computer-readable recording medium

A method for compressing a semiconductor integrated circuit, comprising dividing a design region, in which a semiconductor integrated circuit is to be designed, into a plurality of blocks, assigning semiconductor devices to each of the blocks, determining a device density of each block, compressing any block, and connecting the blocks by wiring. In the compressing of the block, the block that is determined to have a low device density is compressed.

Method for compressing semiconductor integrated circuit, using design region divided into plural blocks

A sign extension unit has first and second sign extenders to extend a sign bit, i.e., the most significant bit of input data to the higher side of the input data. The input data is divided into n-bit blocks. The first sign extender carries out sign extension based on highest bits of the blocks, and the second sign extender carries out sign extension in each of the blocks based on the highest bits of the respective blocks.

Sign extension unit

Upon execution of four sets of m/2 bit&times;n/2 bit multiplication, four multiplicand selectors select m/2-bit multiplicands respectively and four multiplicator selectors select corresponding n/2-bit multiplicators respectively, then the selected m/2-bit multiplicands and n/2-bit multiplicators are input into four multipliers, and then four sets of m/2 bit&times;n/2 bit multiplication are executed in parallel. Upon execution of m bit&times;n bit multiplication, the four multiplicand selectors select upper or lower m/2-bit multiplicands respectively and the four multiplicator selectors select upper or lower n/2-bit multiplicators respectively, then the selected m/2-bit multiplicands and n/2-bit multiplicators are input into the four multipliers respectively, then multiplication results of (lower m/2 bits of m bits)&times;(lower n/2 bits of n bits) and (upper m/2 bits of m bits)&times;(upper n/2 bits of n bits) out of four multiplication results of the four multipliers are connected by a connector, and then the connected multiplication results and the other two multiplication results are added by an adder with arranging in a predetermined bit location each other respectively.

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Kanagawa, Japan

Naoyuki Tamura