Renesas Technology Corp.

Naoyuki Shinonaga

Kazunari Michii

Shinji Semba

Daisuke Ito

Hiroshi Nakagawa

Tetsuya Hirose

Katsutoshi Ito

Shuichi Osaka

Shinji Senba

An interposer substrate having electrodes on the front surface and on the rear surface thereof, respectively, is prepared, and at least one memory chip having electrodes connected to an internal circuit is prepared. Then, the rear surface of the memory chip is bonded to the front surface of the interposer substrate, and the memory chip is sealed to the front surface of the interposer substrate to constitute an encapsulated capsule type semiconductor package. On the other hand, a logic chip is prepared. Further, a main substrate is prepared in which electrodes are formed on the front surface and on the rear surface, respectively, and desired internal connections are provided between these electrodes. Then, the capsule type semiconductor package and the logic chip are laminated on the main substrate, and desired connections are provided between the electrodes on the rear surface of the interposer substrate of the capsule type semiconductor package, the electrodes of the logic chip and the electrodes on the front surface of the main substrate. The capsule type semiconductor package and the logic chip are sealed to the front surface of the main substrate by a resin to obtain a system-in-package type semiconductor device.

Semiconductor device including capsule type semiconductor package and semiconductor chip in stacking manner

A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the corresponding solder balls of adjacent semiconductor chips becomes 'n' times ('n' is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.

Semiconductor device with terminals, and method of manufacturing the same

A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the closest solder balls of adjacent semiconductor chips becomes 'n' times ('n' is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.

A lead frame comprises a plurality of frame assemblies. Each framework assembly includes a framework, a suspension lead, a die pad, a plurality of inner leads and outer leads, a first tie bar and a second tie bar, and a lead support. The plurality of framework assemblies are disposed alongside of one another in a direction perpendicular to a direction in which the plurality of outer leads extend. A distance between close-set outer leads in each two neighboring frameworks is substantially n times a pitch of the plurality of outer leads in each framework, wherein n is an integer.

Lead frame, and method for manufacturing semiconductor device and method for inspecting electrical properties of small device using the lead frame

There is provided a test board for testing semiconductor devices by connecting a plurality of DUTs (semiconductor devices under the test) with a test head, and transmitting test signals from the test head to the plurality of DUTs. The test board comprises a motherboard connected to the test head; a multi-layer wiring board connected to each of the plurality of DUTs; and a scramble board disposed between the motherboard and the multi-layer wiring board. The motherboard and the scramble board, and the multi-layer wiring board and the scramble board are each connected by female connectors and male connectors.

Test board for testing semiconductor device

A connector enabling wiping operation without changing the distance between a male connector and a female connector and capable of changing connectional association by mechanically operating the connector is obtained. The connector includes a male connector having a male connector terminal, a female connector having a female connector terminal, a relay connector terminal movably mounted on either a male connector body or a female connector body and a drive mechanism part bringing the relay connector terminal into contact with both of the male connector terminal and the female connector terminal and performing rubbing.

Growing community of inventors

Nagano, Japan

Naoyuki Shinonaga