Sharp Kabushiki Kaisha Corporation

Naoyuki Shinmura

Katsuji Iguchi

Shigeo Ohnishi

Takashi Nakano

Seizo Kakimoto

Shinobu Yamazaki

Masayuki Tajiri

Tetsuya Ohnishi

Takahiro Shibuya

Shinichi Sato

Takuji Tanigami

Tsukasa Doi

Takayuki Taniguchi

Kenji Hakozaki

Masanori Yoshimi

A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

Structure and manufacturing method of semiconductor memory device

A crosspoint structure semiconductor memory device includes a plurality of upper electrode interconnectings extending in the same direction and a plurality of lower electrode interconnectings extending in a direction orthogonal to the extension direction of the upper electrode interconnectings. A storage material member that stores data is formed between the upper electrode interconnectings and the lower electrode interconnectings. At least either the upper electrode interconnectings or the lower electrode interconnectings are formed along sidewall surfaces of projections formed into stripes of an insulation film processed to have the projections.

Crosspoint structure semiconductor memory device, and manufacturing method thereof

The present invention provides a process for fabricating semiconductor device comprising the steps of: forming an etching-stop layer on a semiconductor substrate; patterning the etching-stop layer so that the etching-stop layer remains in a region to be an active region and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the semiconductor substrate an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer above the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting semiconductor substrate for flattening after removing the resist pattern.

Process for fabricating a semiconductor device

A method of forming a device isolation region includes the steps of: forming a first dielectric film and an oxidation-resistant deposition film successively on a semiconductor substrate; forming a trench groove in the semiconductor substrate by successively processing the oxidation-resistant deposition film, the first dielectric film and the semiconductor substrate by anisotropic etching; forming a second dielectric film to cover at least an inner surface of the trench groove; depositing a third dielectric film in the trench groove so that the thickness of the third dielectric film buried in the trench groove is larger than a depth of the trench groove; planarizing a surface of the third dielectric film and an upper surface of the trench groove; and removing the oxidation-resistant deposition film and the first dielectric film to form the device isolation region, wherein a thermal treatment of the entire substrate is carried out to densify the third dielectric film and to oxidize an interface between the second dielectric film and the semiconductor substrate.

Method of forming a device isolation region

A method of fabricating a semiconductor device is provided which requires less distance allowance between gate electrodes and a contact hole, and which can therefore readily promote micro-fine patterning. A gate insulating film, conductive films to be used as material for gate electrodes, and a mask insulating film to be used as an etching mask are sequentially formed in stack on a surface of a semiconductor substrate. The mask insulating film and the conductive films are processed into a gate electrode pattern. An interlayer insulation film is deposited to fill a space between adjacent stacks of the mask insulating film and gate electrodes. The interlayer insulation film is selectively etched relative to the mask insulating film, thereby exposing sides of the mask insulating film. Side wall films are formed on the exposed portions of sides of the mask insulating film. The interlayer insulation film is selectively etched relative to the mask insulating film and side wall films, a contact hole being thereby formed.

Method of fabricating a semiconductor device including a contact hole

A process for manufacturing a semiconductor device including: forming a mask having a pattern for forming a trench on a semiconductor substrate; forming a film having substantially the same etch rate as the semiconductor substrate on the resulting semiconductor substrate; forming a trench having an inclined sidewall by simultaneously etching the film and a trench formation region on the semiconductor substrate; and embedding an insulating material in the trench thereby to form a device isolation region.

Process for forming a trench device isolation region on a semiconductor

A semiconductor memory device includes a plurality of memory cells each including a transistor formed on a surface of a semiconductor substrate and having one terminal, and a capacitor formed on the semiconductor substrate and having first and second electrodes, with the first electrode being connected with one terminal of the transistor. The first electrode of the capacitor includes a principal portion of either a generally rectangular cubic configuration or a generally cup-shaped configuration, a peripheral portion spaced from and surrounding a peripheral side wall of the principal portion and a bottom portion connecting an end of the principal portion with an end of the peripheral portion. On the other hand, the second electrode of the capacitor includes respective portions confronting the principal portion, the peripheral portion and the bottom portion of the first electrode.

Semiconductor memory device

A semiconductor memory device includes a plurality of memory cells each including a transistor formed on a surface of a semiconductor substrate and having one terminal, and a capacitor formed on the semiconductor substrate and having first and second electrodes, with the first electrode being connected with one terminal of the transistor. The first electrode of the capacitor includes of a principal portion of either a generally rectangular cubic configuration or a generally cup-shaped configuration, a peripheral portion spaced from and surrounding a peripheral side wall of the principal portion and a bottom portion connecting an end of the principal portion with an end of the peripheral portion. On the other hand, the second electrode of the capacitor is includes of respective portions confronting the principal portion, the peripheral portion and the bottom portion of the first electrode.

Growing community of inventors

Fukuyama, Japan

Naoyuki Shinmura