Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Other

Naoyuki Shigyo

Tetsuya Yamaguchi

Toshiyuki Enda

Makoto Yoshimi

Kentaro Watanabe

Kazuya Matsuzawa

Hiroyoshi Tanimoto

Ryo Dang

Takeshi Hamamoto

Akira Nishiyama

Satoshi Inaba

Tohru Ozaki

Atsushi Murakoshi

Masami Aoki

Yoshiaki Matsushita

Kiyomi Naruke

Koichi Sato

Osamu Arisumi

Kazuya Ohuchi

Yutaka Ishibashi

Shigeo Kondo

Mutsuo Morikado

Takeshi Shimane

Takayuki Hiraoka

Akira Toriumi

Minoru Takahashi

Hideto Horii

Mamoru Terauchi

Toshiaki Ikoma

Kunihiro Yamada

Hitomi Kawaguchiya

Sanae Fukuda

Tetsunori Wada

Masami Konaka

Hisayoshi Yanai

Hajime Maeda

Michiru Hogyoku

A memory system includes: a memory chip group including n chips of a nonvolatile semiconductor memory dividedly managed for each of unit areas having predetermined sizes, an unit area of one chip among the n chips storing an error correction code for a group including unit areas in the other n&#x2212;1 chips associated with the unit area, and the chip that stores the error correction code being different for each of positions of the unit areas; and an access-destination calculating unit that designates, when data in the unit areas is rewritten, the unit area in which the error correction code of data is stored as a writing destination of rewriting data, and designates an unit area in which data before rewriting is stored as a storage destination of a new error correction code.

Memory system and computer system

A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor. Thereafter, the programming means applies an intermediate voltage incremented stepwise from the initial intermediate voltage, to one of the respective memory cells adjacent to the programming target memory cell transistor, while applying a constant final programming voltage to the programming target memory cell transistor.

Non-volatile semiconductor memory device and a programming method thereof

According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation layer. A current path functioning as a source region or a drain region of a selected memory cell is formed in the semiconductor substrate when a voltage is applied to the first gate electrode of one of unselected memory cells. The first insulating film is formed on the semiconductor substrate to fill a region between the first gate electrodes of the memory cells adjacent to each other.

Semiconductor memory device including charge accumulation layer

A semiconductor device includes first, second, third, and fourth semiconductor regions, a gate electrode, and silicide layers. The first, second, and third semiconductor regions are formed in a semiconductor substrate while being spaced part from each other. The fourth semiconductor region is formed in the semiconductor substrate between the second semiconductor region and the third semiconductor region and has an electric resistance higher than the first, second, and third semiconductor regions. In a direction perpendicular to a direction to connect the first and second semiconductor regions, the fourth semiconductor region has a width smaller than that of the semiconductor substrate sandwiched between the first semiconductor region and the second semiconductor region. The gate electrode is formed above the semiconductor substrate between the first semiconductor region and the second semiconductor region. The silicide layer is formed on each of the first, second, third semiconductor regions and the gate electrode.

Semiconductor device including overcurrent protection element

A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio &#x394;C/C or a resistance-by-capacitance variation ratio &#x394;(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (&#x3b4;) for the wiring structure, a tolerance (&#x3be;) for the capacitance variation ratio (&#x394;C/C), and a tolerance (&#x3be;) for the resistance-by-capacitance variation ratio (&#x394;(RC)/(RC)), evaluates a fringe capacitance ratio (F=C/C) according to a fringe capacitance Cand parallel-plate capacitance Cof the wiring structure, and determines the wiring structure so that the fringe capacitance ratio (F) may satisfy the following:  The method employs an equivalent-variations condition defined as |&#x394;C/C|=|&#x394;(RC)/(RC)| to determine the shape parameters of each wire of the wiring structure.

Method of designing wiring structure of semiconductor device and wiring structure designed accordingly

A wiring structure of a semiconductor device, includes a wiring layer formed on an insulating film, a width (W) of each wire in the wiring layer and a thickness (H) of the insulating film satisfying 'W/H&#x3c;1' a length (L) of each wiring in the wiring layer being equal to or longer than 1 mm.

There is disclosed a semiconductor device comprising at least one first pad being formed above a substrate and given a first potential, at least one first conductive layer being formed between the first pad and the substrate so as to be electrically connected to the first pad, at least one second pad being formed above the substrate so as to sandwich the at least one first conductive layer between the second pad and the substrate, and given a second potential different from the first potential, at least one second conductive layer being formed between the first and second pads and the substrate so as to be electrically connected to the second pad, and a plurality of insulating layers being stacked on the substrate and at least one of the insulating layers being as an inter-electrode insulator of a capacitance element.

Semiconductor device

A nonvolatile semiconductor memory has memory cells (,) each having an insulated-gate FET that has an information storage part. A semiconductor region (,) is formed at the surface of a channel region of each memory cell. The semiconductor region has the same conductivity type as a channel conductivity type and functions to decrease the strength of an electric field at the surface of the channel region. If the insulated-gate FET is of an n-channel type, the semiconductor region is of an n-type. The semiconductor region suppresses threshold voltage variations among the insulated-gate FETs of the memory cells and prevents soft-writing in the memory cells.

Erasable and programmable nonvolatile semiconductor memory, semiconductor integrated circuit device having the semiconductor memory and method of manufacturing the semiconductor memory

A &Dgr;Z calculator calculates difference between an inversion layer capacitance by a classical theory and an inversion layer capacitance by a quantum theory, calculates &Dgr;Z which is a thickness of a semiconductor substrate equivalent to the difference in inversion layer capacitance. A discretization mesh generator generates a Delaunay discretization mesh for a structure of the semiconductor device to be evaluated. An electrical parameter calculator calculates electrical parameters of the semiconductor device under constraint that a charge density of channel conductivity type of the semiconductor device is set to zero at discretization mesh points of the discretization mesh on an interface between an insulating film and the semiconductor substrate and at discretization mesh points of the discretization mesh in the semiconductor substrate which are located within a distance less than the stored &Dgr;Z from the interface between the insulating film and the semiconductor substrate.

Electrical parameter evaluation system, electrical parameter evaluation method, and computer-readable recording medium for recording electrical parameter evaluation program

A silicon oxide layer serving as an insulation layer is formed on a p-type semiconductor substrate. An n.sup.+ -type source and drain regions are formed on the p-type substrate 110 with a spacing therebetween. A channel region is interposed between the source and drain regions. A silicon oxide layer serving as an insulation layer is formed on the channel region. A gate terminal is formed on the silicon oxide layer. High-concentration p-type regions are formed in the p-type semiconductor substrate under the source and drain regions, respectively.

Method for manufacturing a semiconductor device with ion implantation

A first silicon oxide layer serving as an insulation layer is formed on a p-type semiconductor substrate. An n.sup.+ -type source and drain regions are formed on the p-type substrate 110 with a spacing therebetween. A channel region is interposed between the source and drain regions. A second silicon oxide layer serving as a gate insulation layer is formed on the channel region. A gate terminal is formed on the second silicon oxide layer. High-concentration p-type regions are formed in the p-type semiconductor substrate under the source and drain regions, respectively.

Semiconductor device of a silicon on insulator metal-insulator type with

A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

Insulated-gate transistor having narrow-bandgap-source

In a semiconductor device having a thin SOI film, the thickness of a semiconductor layer formed on an insulating film is so adjusted as to be less than a maximum distance allowable to complete depletion of the layer. While the thickness of a channel region is adjusted to be less than that of impurity-diffusion regions. Further, the insulating layer is so formed to have a thicker portion under the channel region, and thinner portions under the source region and the drain region as the impurity-diffusion regions. The semiconductor layer has steps at the boundaries between the channel region and the impurity-diffusion regions, and the top face of the channel region is arranged so as to be lower than the top faces of the impurity-diffusion regions. A region having a width less than the maximum depletion distance and an impurity concentration larger, than that of the channel region and less than that of the drain region is formed between the channel region and the drain region.

Semiconductor device having a single crystal semiconductor layer formed

A semiconductor memory device, in particular a dynamic random access memory cell which realizes a high speed thereof and presenting a superior controllability. The dynamic random access memory (DRAM) cell includes: a first transistor; a second transistor, electrically connected in series to the first transistor, for storing an electric charge, the second transistor including a portion for erasing the charge stored at the second transistor, wherein the first transistor and the second transistor are electrically connected between a power line and a bit line; and a diode electrically connected between the first transistor and the second transistor. Alternatively, the present invention can be realized with three transistors where the memory cell includes: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series at a connecting node therebetween; and a third transistor provided between a gate of the first transistor and the connecting node, wherein a gate of the second transistor and a gate of the third transistor are commonly connected to the word line.

Growing community of inventors

Yokohama, Japan

Naoyuki Shigyo