Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Naoyuki Komuta

Masatoshi Fukuda

Soichi Homma

Atsushi Yoshimura

Hideo Numata

Yukifumi Oyama

Hiroshi Watabe

Yuji Karakane

Satoshi Tsukiyama

Keita Mizoguchi

Hideo Aoki

Masayuki Miura

Kanako Sawada

Shinya Fukayama

Yuka Akahane

Koji Ogiso

A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.

Semiconductor device manufacturing method

A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.

Semiconductor device and manufacturing method thereof

A method for manufacturing a semiconductor device including a plurality of semiconductor chips includes steps of placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip, determining a distance between the first semiconductor chip and the second semiconductor chip, and determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.

Method and apparatus for manufacturing a semiconductor device including a plurality of semiconductor chips connected with bumps

A manufacturing apparatus of a semiconductor device includes a stage, a head unit configured to face the stage, a driving unit configured to move the head unit towards and away from the stage, a heating unit configured to heat the head unit, and a control unit configured to control the driving unit to move the head unit away from the stage when the heating unit heats the head unit.

Apparatus and method for manufacturing semiconductor device

A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.

Method for manufacturing electronic component and manufacturing apparatus of electronic component

A first semiconductor chip has a first electrode pad, and a second semiconductor chip has a first through via and a second electrode pad joined to the via and aligned with the first electrode pad. A third semiconductor chip has a second through via, a third electrode pad joined to the via, wiring joined to the via, and a fourth electrode pad joined to the wiring and aligned with the second and third electrode pads. The semiconductor chips are stacked and electrically connected by joining the first to third electrode pads to one another, and gaps of the stacked body are filled with resin. The stacked body is secured to an adhesive material formed on a substrate and a solder bump formed on the substrate is joined to the fourth electrode. A molding resin encapsulates the stacked body and an adjacent surface of the substrate.

Method for manufacturing semiconductor device and semiconductor device

In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips.

An apparatus relating to the manufacture of stacked semiconductor devices includes, for example, a first holding section configured to hold a first semiconductor device and a second holding section configured to hold a second semiconductor device. Additionally, a measuring section including an imaging device for acquiring images of the first and second semiconductor devices and a control section configured to control the holding sections to correct misalignment between the semiconductor devices. The control section is further configured to determine misalignment using the images of the first and second semiconductor devices when the images include a first alignment mark disposed proximate to an edge of the first semiconductor device and a second alignment mark disposed proximate to an edge of the second semiconductor device.

Inspection apparatus and inspection method for semiconductor device

A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.

Stacked electronic component and manufacturing method thereof

In one embodiment, a first substrate having first solder bumps and a second substrate having second solder bumps are stacked while temporarily tacking the solder bumps to each other, and then a stack is disposed inside a furnace. The gas in the furnace is exhausted to be in a reduced pressure atmosphere, and then a carboxylic acid gas is introduced into the furnace. While increasing a temperature inside the furnace where the carboxylic acid gas is introduced, the gas in the furnace is exhausted to be in a reduced pressure atmosphere at a temperature in a range from a reduction temperature of oxide films by the carboxylic acid gas to lower than a melting temperature of the solder bumps. By increasing the temperature inside the furnace up to a temperature in a range of the melting temperature of the solder bumps and higher, the first solder bumps and the second solder bumps are melted and joined.

Growing community of inventors

Oita, Japan

Naoyuki Komuta