Mitsubishi Denki Kabushiki Kaisha

Naoyuki Kato

Hiroshi Komurasaki

Hisayasu Satoh

Tetsuya Iga

Hideyuki Wakada

In a variable frequency divider formed of a latch train, a frequency division ratio is set through selective invalidating a feedback signal to a first stage latch from the last stage latch. A size of MOS (metal-insulator-semiconductor) transistors for switching the division ratio is made larger than that of other MOS transistors in differential stages in the last stage latch circuit. Further, differential signals are transmitted as feedback signals to the first stage latch circuit. A F/(F&plus;1) prescaler which operates stably with a low current consumption under a low power supply voltage condition is implemented.

Variable frequency divider circuit

There is disclosed a PLL circuit wherein a delay circuit (3') of a phase comparator (30') receives a supply current (IC) from a first variable current source (.PHI.IC) and changes a delay time (.DELTA.T) in negative correlation with the amount of the supply current (IC), and the first variable current source (.PHI.IC) changes the amount of the supply current (IC) to the delay circuit (3') in accordance with the indication of a control signal (C1) serving as a supply current control signal for a second variable current source (.PHI.IA) and a third variable current source (.PHI.IB) of a charge pump circuit (31). Changes in delay time of the delay device of the phase comparing device are adapted such that the delay time is constantly suitable as the amount of current of the phase comparison voltage signal of the charge pump circuit changes, permitting reduction in lock-up time.

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Hyogo, Japan

Naoyuki Kato