Kabushiki Kaisha Toshiba

Asahi Kasei Kabushiki Kaisha

Kosumi LLC

Naoyuki Kai

Masahide Ohhashi

Tsutomu Minagawa

Yukimasa Uchida

Yoshiharu Uetani

Akiyasu Funakawa

Haruya Iwata

Yoshifumi Kado

Ichiro Nagashima

Sohei Iiyama

It is desirable to process a header by a processor for flexible processing in a stream data processing device. However, in the processing by the processor, load/store overhead increases and causes a problem in performance. Stream data is directly written to or read out from a large size data queue, a part of which is mapped to a region (window) of a general-purpose register of the processor. Imposing constraints on update of a pointer of the queue makes it possible to ensure that a large-small relationship between pointers can be constantly correctly evaluated, and thus to maintain the consistency between write to and read from the queue and the processor processing. A region, which is the same as the data queue, has a control flag queue mapped to a control and status register space of the processor, and the processor gives this control flag, so that an output from the queue is finely controlled without copying the data.

Processor including a stream interface and system

Electrode structure, method for producing electrode structure, electrolytic cell, and electrolyzer

An image decoding apparatus obtains the prediction error or a restored image of the encoding object image by inverse processing of the encoding processing of encoded image data encoded by motion compensation predictive coding, in which a restored image is obtained by adding the prediction error and a reference image, a reduced size image of the restored image is generated and stored along with the restored image; wherein, when an image is encoded by an encoding mode that uses reference pixels that include two times or more number of pixels of a region of a predetermined number of pixels, a reference image is obtained by reading out and expanding the stored reduced size image of the restored image, and when an image is encoded using reference pixels of less than two times a number of pixels of the predetermined number of pixels, the reference image is obtained from the stored restored image.

Image decoding apparatus and image decoding method

Coded image data having a DTS (decode time stamp) appended for each frame are written into an input buffer. A portion of the storage area of the input buffer is scanned to produce identification information (ID) for each frame of image data. For each frame of image data, the ID, DTS, storage location in the buffer and coding type are held in the form of a mapping table. The system time clock (STC) is compared with the DTSs in the table. When a match occurs, the storage location for the corresponding frame of image data is read from the table and sent to a decoder, which in turn reads the corresponding image data from the buffer and decodes it.

Image processing device, television receiver and image reproducing device

A pattern generation scheme is initiated by abstaining flag information for filling a pattern is obtained from data of an outline quantized on a bit map. The flag information of the outline is written in a work memory for filling, and a filling pattern is obtained in a scanning direction on the bit map. When a drawing point for filling is present outside a work area of the work memory and in scanning start direction on a scan line, a flag for filling is written in a scanning start point in the work area. Even when the outline overflows the work area, a pattern for correctly filling the interior of the outline in the work area can be generated.

Filling pattern generation apparatus and method including correction for

A painting pattern generation system for painting interior areas enclosed by outlines indicated by outline data and flag data. This includes a first memory for storing outline data, a second memory for storing flag data, and an operational circuit for reading out the outline data. The flag data in the first and the second memories performs a logical exclusive OR operation on adjacent items of the flag data in the second memory in a scan line direction, and performs an OR operation between the result of the logical exclusive OR operation and the outline data in the first memory in all of the scan line directions. Thus obtaining the painted pattern data, and a writing circuit for writing the painted pattern data obtained by the operational circuit to overlap it with subsequent outline data in the first memory.

Painting pattern generation system using outline data and flag data

A stack memory for high-speed operation comprises a RAM for storing data and a stack pointer for holding an address of the PUSH data. The POP data are always stored in an address smaller by '1' than the address for storing the PUSH data. According to this stack memory, both reading the POP data and storing PUSH data is simultaneously executed, then the one of them can be validated. Thus, it becomes possible to execute the access to the RAM before the data process mode is decided.

High-speed stack memory

Coordinate values of control points of a given Bezier curve are stored in a register, the contents of the register are supplied to a determination circuit to determine whether a distance between adjacent control points can further be bisected into two parts. If bisecting processing can be performed, the contents of the register are supplied to a bisection circuit, the Bezier curve is subdivided into two parts to generate new Bezier curves, and control point data of one of the new Bezier curves is applied to a stack memory and that of the other new Bezier curve is sent to the register. The contents of the register are checked by the determination circuit each time the contents of the register are updated.

Apparatus for generating an arbitrary parameter curve represented as an

A pattern data generating system has a processor for writing in a bit map memory, on the basis of input data, points of all lines to be filled or painted along a scan direction which is one direction on the bit map memory. This writing is performed such that a point on each line is written as one of the two end points of the line thereof while a point, offset by one point in the scan direction, is written as the other of the two end points of the line. The pattern data generating system also has a pattern data generating circuit for, if w (w is a positive integer) points b0, b1, . . . , b(w-2), and b(w-1) are present on one scan line, writing EXOR of data of points b0, b1, . . . , b(j-1) at positions corresponding to points b(j) (j is not less than 0 and less than w). Similar EXOR data writing is performed by the pattern data generating circuit for all the scan lines. Then, pattern data, in which the area surrounded by the closed curve is filled or painted, is obtained.

Pattern data generating system

A bit mask generator comprises partial mask generators for generating partial mask data corresponding to a plurality of blocks obtained by dividing input data, and parity correction circuits for correcting the partial mask data in accordance with a parity input and generating parity outputs. Each of the partial mask generators includes a plurality of first exclusive OR gates each of which receives bit data of a corresponding block as one input and input data of an LSB (Least Significant Bit) or an output of a lower-bit first exclusive OR gate as the other input. Each of the parity correction circuits includes a plurality of second exclusive OR gates each of which receives as one input the partial mask data generated by the partial mask generator of a corresponding block and as the other input a parity generated by a lower-bit parity correction circuit. An output from each second exclusive OR gate is generated as mask data of the corresponding block, and an output from the MSB (Most Significant Bit) second exclusive OR gate is generated as the parity.

Bit mask generator

A pattern data generating system comprises first and second bit map memories, a first control block for sequentially generating points corresponding to the boundaries of a closed curve in response to changes dx and dy along x and y directions, and writing the points in the first bit map memory, a second control block for sequentially generating points, which are required to paint an area enclosed by the closed curve, on the basis of the changes dx and dy, in accordance with a predetermined rule, and writing the points in the second bit map memory, a third control block for, if w (w is a positive integer) points b0, b1, . . . , b(w-2), and b(w-1) are present on a single scan line provided that one direction is set to be a scan direction on the second bit map memory, sequentially writing EXOR data of the points b0, b1, . . . , b(j-1) (j is not less than 0 and less than w) at positions corresponding to points b(j), and a fourth control block for obtaining pattern data by final filling or painting in which an arithmetic operation (e.g., logical OR or logical AND) of data of an arbitrary point in the first bit map memory with data of a corresponding point in the second bit map memory which stores the EXOR data is performed.

A memory device having an operating function includes a memory cell array, a register, and a logical opeation circuit. The memory cell array has memory cells arranged in a matrix form of m rows .times.n columns. Data readout or write-in operation with respect to the memory cell array is effected in the unit of n bits of one row. The register has a bit width corresponding to one row of the memory cell array. Data of one row is read out from the memory cell array and is processed by the logical operation circuit together with data stored in the register. The result of operation is written into a desired row of the memory cell array. The memory cell array, register, and logical operation circuit are formed in the same integrated circuit, thus permitting processing such as picture element processing to be effected inside the integrated circuit, without the need to use an external data bus.

Memory device having operating function

A semiconductor memory device includes a column decoder which is constructed such that it selects two adjacent columns in a memory cell array, and by means of which one of the two columns at a higher or lower position is selected, depending on whether or not a control signal indicates that one is added to a designated address. When the designated column address is the most significant address, the most and least significant addresses are selected, and if, in this case, the control signal indicates that one is added to the designated address, the least significant column address is selected and an address carry signal is generated. If, on the other hand, the control signal indicates that one is not added to the designated address, then the most significant column address is selected, in which case no address carry signal is generated. Similarly, a row decoder is constructed such that it selects two adjacent rows in the memory cell array, and one of the two columns at a higher or lower position is respectively selected, depending on whether or not an address carry signal is generated from the column decoder. When the designated row address is the most significant address, the most and least significant addresses are selected, and if, in this case, the address carry signal is generated from the column decoder, the least significant row address is selected, while if the address carry signal is not generated, then the most significant row address is selected.

Semiconductor memory device

A semiconductor memory device comprises an address signal generator for generating address signals including row and column address signals, and an additional address signal to indicate if the column address is even- or odd-numbered; even- and odd-numbered bank memories with a plurality of word areas each including n bit areas; row decoder which in response to a row address signal, specifies the row address position in the even- or odd-numbered bank memory; and a column decoder which in response to the address signal, specifies the column address positions in the even- and odd-numbered bank memories. The column decoder responds to the address signal representing the column address 2j or (2j+1), to specify the column address position [2j] or [2j+2] in the even-numbered memory, and at the same time specifies the column address position [2j+1] in the odd-numbered bank memory.

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Tokyo, Japan

Naoyuki Kai