Hitachi Ulsi Systems Co., Ltd.

Hitachi, Ltd.

Naoyuki Anan

Keiichi Higeta

Michitaro Kanamitsu

Takashi Koba

Masami Hasegawa

Seryung Park

Yayoi Hayashi

Masayuki Hirayama

Mikiko Sakai

A circuit system is provided capable of improving the throughput thereof by eliminating the operational constraint that if the operating frequency of a content addressable memory is lower than the operating frequency of a system LSI, two system clocks should be provided, or the higher frequency should be synchronized with the slower system clock. A clock control circuit () for down-converting an internal clock (&#x3a6;) of a LSI () is provided, and a control signal whose frequency is made lower is used to operate a content addressable memory circuit ().

Semiconductor integrated circuit and image processing system using the same

A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto.

Semiconductor device

Growing community of inventors

Ome, Japan

Naoyuki Anan