Adv Antest Corporation

Toei Scientific Industrial Co., Ltd.

Naoyoshi Watanabe

Katsumi Ochiai

Hiroshi Tsukahara

Yokichi Hayashi

Masuhiro Yamada

Ryoichi Utsumi

Shigeyuki Sato

Jun Hashimoto

Satoshi Sudou

Tasuku Fujibe

Kuniyuki Kaneko

Mashuhiro Yamada

A test apparatus tests a wafer under test on which devices under test each including magnetoresistive memory or a magnetic sensor are formed. In a test process, the wafer under test is mounted on a stage. In the test process, a magnetic field application apparatus applies a magnetic field Bto the wafer under test. A test probe card is used in the test process. Multiple magnetization detection units are formed on a diagnostic wafer. In a diagnostic process of the test apparatus, the diagnostic wafer is mounted on the stage instead of the wafer under test. Each magnetization detection unit is capable of measuring a magnetic field Bgenerated by the magnetic field application apparatus. In the diagnostic process, the diagnostic probe card is used instead of the test probe card.

Test apparatus

The test apparatus tests a wafer under test on which devices under test each including magnetoresistive memory or a magnetic sensor are formed. In a test process, the wafer under test is mounted on a stage. A test probe card is configured such that it can make probe contact with the wafer under test in the test process. A wafer connection HiFix is arranged between the test probe card and a test head. A magnetic field application apparatus is provided to the wafer connection HiFix. In the test process, the magnetic field application apparatus applies a magnetic field Bto the wafer under test.

Provided is a test apparatus that tests a device under test having a plurality of output terminals. The test apparatus comprises an executing section that executes a test command sequence for testing the device under test; a storage section that stores a plurality of pieces of setting data designating one or more output terminals among the plurality of output terminals; a detecting section that detects whether a value of an output signal from an output terminal designated by one of the pieces of setting data matches an expected value; and a selecting section that selects different pieces of setting data in the storage section when at least two detection commands, which change execution sequencing of the test command sequence according to the detection results of the detecting section, are executed, and supplies the selected pieces of setting data to the detecting section.

Test apparatus and test method

There is provided a test apparatus for testing a memory under test that is addressable by the number of pulses of an address signal supplied thereto. The test apparatus includes a pattern generating section that generates writing data to be written into the memory under test, a first address generating section having an address information storing section that stores thereon address information indicating an address of the memory under test to which the writing data is to be written, and a waveform shaping section that generates an address signal by outputting one or more pulses at a predetermined time interval during a time period determined in accordance with the address information stored on the address information storing section.

Testing device, testing method, computer program product, and recording medium

In a semiconductor device testing apparatus for testing a plurality of semiconductor devices at one time, data peculiar to each semiconductor device can be written therein simultaneously with the avoidance of excessive enlargement in the scale of circuitry. A pair of an integer delay generation part and a fraction delay data generation part that are components of the semiconductor device testing apparatus is provided by the same number as that of pins of each semiconductor device under test, and a waveform control part is provided by the same number as that of the semiconductor devices under test for each of the pairs. In each waveform control part are generated a set pulse and a reset pulse for generating a test pattern signal to be applied to each of pins having the same attribute of the semiconductor devices under test, thereby to generate a test pattern signal. By applying individual data to each waveform control part instead of test pattern data, respective individual data can be written simultaneously in the semiconductor devices under test.

Semiconductor device tester

A waveform generating apparatus capable of outputting a desired waveform is provided. Among delay data is selected a set pulse generating delay data depending on test logical data and waveform mode information. The delay data, a skew adjusting delay data, and a fraction data in each test cycle are computed to obtain an integer delay data and a fraction delay data, which are supplied to a counter delay circuit. From the counter delay circuit are outputted a set pulse generating effective flag for delaying a test period timing by a delay time corresponding to the integer delay data, and a fraction delay data related thereto. The effective flag is delayed based on the related fraction delay data to obtain a set pulse. Similarly with the set pulse, a reset pulse is obtained, thereby to set/reset an S-R flip-flop to output a desired waveform.

Waveform generating device

A timing signal generating apparatus capable of automatically detecting any erroneous set state that a pulse duration of a test pattern signal and a time duration between adjacent two pulses of the test pattern signal have been set in a program with the durations being shorter than corresponding limit values respectively, and a method of detecting any set error to the program for a timing signal. At the outside of a clock generator,A for generating a set pulse P,and a reset pulse P,are provided a fourth latch circuit,for latching therein an integer delay signal MT outputted from a down-counter,of an integer delay giving device,, and a fifth latch circuit,for latching therein an odd value MDAT outputted from a first latch circuit,of the integer delay giving device,, thereby to detect a time duration from the set pulse until the reset pulse or a time duration from the reset pulse until the set pulse. If the time duration is shorter than a limit value WMT,or WMT,, a logical signal indicating a set error is generated.

Timing signal generating apparatus and method

A fine variable delay circuit includes a buffer having an input connected to a signal input terminal and an output. The buffer has an output impedance and outputs a logical level from the output. The fine variable delay circuit also includes a schmidt trigger buffer having an input connected to the output of the buffer and an output connected to a signal output terminal, a CMOS transistor having a gate and two electrodes, the gate being connected to a connection point between said buffer and said schmidt trigger buffer. In addition, the fine variable delay circuit includes a first switching element connected between one of the electrodes of the CMOS transistor and one terminal of a power supply, a second switching element connected between another of the electrodes of the CMOS transistor and another terminal of the power supply, and a delay setting circuit responsive to a select signal for controlling the first switching element and the second switching element to set simultaneously each of the first switching element and the second switching element to one of an ON and an OFF state, thereby setting a delay.

Variable delay circuit

First and second exclusive-OR gates (hereinafter referred to as EXOR gates) are provided, which are both connected at one input side to a delay input terminal. The other input side of the first EXOR gate is grounded and the other input side of the second EXOR gate is connected to a select signal input terminal. A capacitor is connected between the output side of the first EXOR gate and the output side of the second EXOR gate. The output side of the first EXOR gate is connected to a delay output terminal by way of a buffer which outputs logical levels. The buffer has a threshold value and outputs one or the other binary logical level depending on whether the input thereto is above or below a threshold value.

The gate of a CMOS transistor formed by a series connection of p-channel and n-channel FETs 21 and 22 is connected to an input terminal 23, and the drain of the CMOS transistor is connected to an output terminal 24. The source of the FET 21 is connected to a positive power supply terminal 20 via parallel-connected switchable resistance elements 37.sub.0, 37.sub.1, 37.sub.2, . . formed by p-channel FETs and having resistance values R.sub.0, R.sub.1, R.sub.2, . . . , respectively. The source of the other FET 22 is connected to a negative power supply terminal 30 via parallel-connected switchable resistance elements 38.sub.0, 38.sub.1, 38.sub.2, . . . formed by n-channel FETs and having resistance values R.sub.0, R.sub.1, R.sub.2, . . . , respectively. Delay setting signals S.sub.0, S.sub.1, . . . are decoded by a decoder 39 and one of more of its output terminals Y.sub.0, Y.sub.1 , . . . go to the high level. The output terminals Y.sub.0, Y.sub.1, Y.sub.2, . . . are connected directly to the gates of the FETs forming the resistance elements 38.sub.0, 38.sub.1, 38.sub.2, . . . , respectively, and are connected to the gates of the FETs of the resistance elements 37.sub.0, 37.sub.1, 37.sub.2, . . . via inverters. The time constant of the charge and discharge for a load capacitance at the output terminal 24 differs with combinations of two resistance elements which are simultaneously turned ON, changing a delay of the input signal accordingly.

A timing generator for generating arbitrarily delayed pulses, in which, upon each readout of period data from a period data memory, a computing section subtracts its accumulated value from delay data read out of a delay data memory, and upon inversion of the sign of the subtracted value, the immediately preceding subtracted value is provided to a delayed pulse generator, which generates a pulse at the timing corresponding to the subtracted value applied thereto.

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Tokyo, Japan

Naoyoshi Watanabe