Kioxia Corporation

Naoya Yoshimura

Keisuke Nakatsuka

Satoshi Nagashima

Yefei Han

Weili Cai

A semiconductor storage device includes first conductive layers stacked in a first direction and extend in a second direction; second conductive layers stacked in the first direction and extend in the second direction; third conductive layers that are electrically connected to the first conductive layers and the second conductive layers and stacked in the first direction; a first insulating layer and a second insulating layer sandwich the first conductive layer; a third insulating layer and a fourth insulating layer sandwich the second conductive layer; first pillars arranged in the second direction in the first insulating layer with a first distance; and second pillars arranged in the second direction in the second insulating layer with the first distance. Each of the second pillars is displaced from a corresponding one of the first pillars by a second distance that is shorter than a half of the first distance in the second direction.

Semiconductor storage device

A semiconductor memory device includes a first pillar. The first pillar includes a first portion and a second portion. The first portion includes a first semiconductor layer and a first insulating film on a side surface of the first semiconductor layer. The first pillar includes a first region that faces the first portion and a second region other than the first region. The second portion includes a first conductive film that is in contact with the first insulating film and a second insulating film. The second insulating film has a first thickness in a fourth direction within the second region and a second thickness in the second direction within the first region. The first thickness is greater than the second thickness.

Semiconductor memory device and method of manufacturing semiconductor memory device

According to one embodiment, a semiconductor storage device includes a semiconductor pillar including a channel. The channel includes a first channel portion and a second channel portion. A virtual cross section intersecting a first direction and including a first interconnection, a first electrode, the semiconductor pillar, a second electrode, and a second interconnection is determined. Both first end portions of the first channel portion and a first midpoint between both the first end portions are determined in the virtual cross section. Both second end portions of the second channel portion and a second midpoint between both the second end portions are determined in the virtual cross section. In this case, an angle between a second direction and a center line connecting the first midpoint and the second midpoint is an acute angle.

A semiconductor memory device according to an embodiment includes a substrate, first to eleventh conductive layers, first and second pillars, and first to fourth insulating regions. The first insulating regions are provided between the third and fifth conductive layers and between the fourth and sixth conductive layers. The second insulating regions are provided between the eighth and tenth conductive layers and between the ninth and eleventh conductive layers. The third insulating region is provided between the third to sixth conductive layers and the eighth to eleventh conductive layers. The fourth insulating region is provided between the second and seventh conductive layers. The fourth insulating region is separated from the third insulating region in a planar view.

Growing community of inventors

Kuwana Mie, Japan

Naoya Yoshimura