Oki Semiconductor Co., Ltd.

Oki Electric Industry Co., Ltd.

Adv Antest Corporation

Lapis Semiconductor Co., Ltd.

Naoya Kimura

Tetsuro Hara

Takayuki Shimizu

Akira Kondo

Haruyo Takayanagi

Shinichi Satoh

Hiroyoshi Ichikura

Seiichirou Ishimoto

Yoshihiro Kato

Yuki Watanabe

Yoshikazu Nakayama

Hiroyuki Konno

Masato Haruta

Shuji Furuichi

Hideaki Odagiri

Yuichiro Harada

Tomoyuki Itakura

Kazuhiro Iezumi

Shuichi Inage

Kazuhiro Tsujikawa

Hiroyoshi Ichkura

Koji Miyauchi

Kunio Takamatsu

Yuichi Arata

Keisuke Kusunoki

A test apparatus is configured to test a DUT that does not support synchronous control from an external circuit. A main controller is configured based on an architecture that tests a device by synchronous control with the main controller itself as the master. A MIU is configured as an interface between the main controller and the DUT. The MIU establishes asynchronous control between it and the DUT with the DUT as the master, and establishes control between it and the main controller with the main controller as the master.

Test apparatus and test method

A display includes capacitive display elements, output drivers, scan switches, precharge switches, and a precharge stopper. The drivers provide drive currents or voltages corresponding to display data, thereby driving the display elements correspondingly to the data. The precharge stopper determines whether display data corresponds to a specific state and prevents the display element from being precharged when the display data corresponds to the specific state.

Display apparatus having precharge capability

A display device includes a controller detecting a black line, in which all light emitting diodes in one line are non-luminescence, counting a number of times (S) that display data indicating the black line is sent to the display panel in serial, halting a scanning operation to the display data indicating the black line, applying the time period for halting the scanning operation to another time period for displaying display data, which are next to the display data indicating the black line and which is not the display data indicating the black line, whereby the another time period for displaying display data is set to 'S+1' times longer than a stipulated time period, and sending a control signal to a column driver, which controls the column driver to set a drive current or voltage applied from a power source to a 1/(S+1) of the stipulated value for the 'S+1' time period.

Display device and method of displaying image

A display panel driver has two driver circuits that drive separate halves of a display panel. Each driver circuit occupies a separate integrated circuit chip. The driver has a screen saving mode in which each driver circuit displays an independent screen saving image that moves in synchronization with a timing signal. The timing signal is generated in one driver circuit and transmitted by a chip-to-chip interface to the other driver circuit. The two screen saving images are thereby coordinated to create what appears to be a single screen saving display.

Dual scan display panel driver

The object of the invention is elimination of an occurrence of instantaneous light in the center part of a display, a border between the upper half and the lower half of the display. An scanning method of the display, dividing the display panel to a first filed and a second filed, starts a counter therein, synchronized with the timing of driving a first row electrode of the first filed thereof, and drives a first row electrode of the second filed thereof, every time the counter value changes.

Scanning method of display panel and a display unit

A color balancing circuit for a flat panel display such as an electroluminescent display generates a primary current that can be varied to adjust the overall brightness of the display. Three currents related to the primary current by selectable ratios are generated, by current mirror circuits, for example; the ratios can be individually varied to adjust the color balance. Driving currents are generated from the three adjusted currents, by mirroring the adjusted currents, for example, and are used to drive display elements that emit light in the three primary colors. Image brightness and color balance can accordingly be adjusted separately, even though both are adjusted by adjusting the driving current. Circuit size is reduced in that the same primary current is used for all three primary colors.

Color balancing circuit for a display panel

Disclosed is a drive circuit for a panel display device for driving light-emitting devices arranged at respective intersections between a plurality of data lines and a plurality of scan lines. This drive circuit includes a voltage control circuit for charging the light-emitting devices to a voltage necessary for light emission by connecting the data lines to a predetermined power supply potential in a rising period prior to a period for selectively causing the light-emitting devices to emit light; and a drive control circuit for selectively connecting the data lines to a constant current source after the rising period.

Drive circuit and drive method for panel display device

There are measured characteristics of a jig (fixture) used to calculate and measure circuit parameters of a device under test. There is provided a jig characteristic measuring device which measures the jig characteristics of a jig which includes signal lines used to connect a DUT and a network analyzer with each other (namely, the reflection characteristics of the signal lines, and the transmission S parameters), measures the reflection coefficients of the signal lines in an open state where the DUT is not connected to the signal lines measures the reflection coefficients of the signal lines in a short-circuit state where all the signal lines are grounded, and derives the jig characteristics of the jig based on these measured results.

Fixture characteristic measuring device, method, program, recording medium, network analyzer, and semiconductor test device

A semiconductor storage device has a simple control circuit that is added to a general one-port RAM. Taking a port-A clock signal as the reference, the control circuit generates a select signal that selects a port A during the period from elapse of a first predetermined time from the reference timing until a second predetermined time has elapsed and selects a port B during other periods. The control circuit generates a port-A delayed clock signal in the period in which the port A is selected. The control circuit generates a port-B delayed clock signal during the period from elapse of the second predetermined time until a third predetermined time has elapsed. The control circuit generates a conflict monitoring signal during the period from the reference timing until the second predetermined time has elapsed. When a clock signal is supplied from the port B while the conflict monitoring signal is being generated, the port-B delayed clock signal is masked while the conflict monitoring signal is being generated. After the conflict monitoring signal is stopped, the B-port delayed clock signal is generated as a port-B clock signal.

Semiconductor storage device

A receiver includes a channel-matched-filter for outputting a Rake-combining result from a digital spread spectrum signal; a carrier recovery circuit which removes an offset of a carrier wave from the combining result; a correlation circuit which detects correlation; a symbol timing detection circuit which extracts a symbol from the correlation; a symbol determination circuit which regenerates data from the symbol; a framer circuit which discriminates a frame configuration; and a symbol timing recovery circuit which generates a timing phase for each of symbol timings. The channel-matched-filter performs multi-phasing compensation and, in accordance with a timing phase from the symbol timing recovery circuit, performs synchronization tracking.

Receiver for spread spectrum communication

Clock switching circuitry includes a memory having a plurality of storage locations of a particular address each and configured to allow data to be written in and read out at the same time. The circuitry further includes a write pointer, a read pointer, a synchronizing circuit, a conflict detector, and a conflict avoiding circuit. The circuitry detects a conflict with high reliability and facilitates design using a CAD (Computer Aided Design) tool.

Clock switching circuitry for avoiding conflict of data handling occuring in a memory

A circuit for detecting abnormality of a subject clock signal, includes a frequency dividing circuit for frequency-dividing a monitoring clock signal to provide a frequency-divided monitoring clock signal; a shift register which stores the frequency-divided monitoring clock signal in synchronization with the subject clock signal; and a plurality of abnormality evaluation circuits. The abnormality evaluation circuits operate complementarily each other in accordance with an output signal of the shift register and detect abnormality of the subject clock signal for a period of time corresponding to the cycle of the monitoring clock signal.

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Chiba, Japan

Naoya Kimura