Renesas Electronics Corporation

Nec Corporation

Ricoh Company, Ltd.

Naoya Inoue

Yoshihiro Hayashi

Kishou Kaneko

Ippei Kume

Kenichiro Hijioka

Hiroshi Sunamura

Makoto Ueki

Jun Kawahara

Manabu Iguchi

Kenzo Manabe

Hiroki Shirai

Akira Tanabe

Toshitsugu Sakamoto

Daisuke Oshida

Hiroto Ohtake

Takuya Maruyama

Hisao Kawaura

Hiroyuki Kunishima

Naoya Furutake

Toshiji Taiji

Takeshi Toda

Masayoshi Tagami

Sota Kobayashi

Hirokazu Katsuyama

The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.

Semiconductor device with electro-static discharge protection device above semiconductor device area

An information processing apparatus includes a receiving unit configured to receive request data to an application via a global network allocated to the information processing apparatus, the request data including a global address specified as a destination address; a determination unit configured to determine, based on the request data, whether the application is to be executed by another apparatus connected via a private network and allocated with a private address; a change unit configured to change the destination address in the request data from the global address of the information processing apparatus to the private address of the another apparatus when the determination unit determines that the application is to be executed by the another apparatus; and a transmission unit configured to transfer, to the another apparatus, the request data including the private address of the another apparatus as the destination address.

Information processing apparatus, relay method, and computer-readable storage medium

A semiconductor device production method includes forming a transition metal film, irradiating a surface of the transition metal film with a mono-silane gas to form a silicon-containing transition metal film, and oxidizing the silicon-containing transition metal film by an oxygen plasma treatment, thereby forming a transition metal silicate film.

Semiconductor device comprising capacitive element

The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.

Method for manufacturing a semiconductor device

An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.

Method of manufacturing a semiconductor device

The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Semiconductor device manufacturing method

The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film.

Method of manufacturing semiconductor device

A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.

Semiconductor device

A method for forming a semiconductor device that includes a SiARC layer formed over a photoresist film which is formed over spacer portions which are formed on a spacer assist layer which is formed over a hard mask layer. The SiARC layer has an etch rate substantially similar to the etch rate of the spacer assist layer. The photoresist layer and the SiARC layer are removed from a first region to expose the spacer portions and the spacer assist layer. The SiARC layer in the second region and the exposed spacer assist layer in the first region are simultaneously etched leaving remaining spacer portions and remaining spacer assist layer portions. A part of the hard mask layer is etched to form hard mask portions in the first region using the remaining spacer portions and the remaining spacer assist layer portions as an etching mask.

Patterning process method for semiconductor devices

A semiconductor device including a semiconductor substrate, a first insulating layer formed over said semiconductor substrate, first grooves formed in said first insulating layer, a gate electrode and a first interconnect filled in said first grooves, respectively, a gate insulating film formed over said gate electrode, a semiconductor layer formed over said gate insulating, a second insulating layer formed over said semiconductor layer and said first insulating film, a via formed in said second insulating layer and connected to said semiconductor layer, a second groove formed in said second insulating layer, and a second interconnect filled in said second groove, formed over said via and connected to said via.

A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

Semiconductor device and manufacturing method therefor

A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.

Semiconductor device with contacts and metal interconnects and method of manufacturing the semiconductor device

There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics.

Growing community of inventors

Kanagawa, Japan

Naoya Inoue