Canon Kabushiki Kaisha

Naotsugu Itoh

Ken Achiwa

Tomohiro Tachikawa

An information processing apparatus that achieves both power supply to an external device and information processing. Power supply capability to be presented to the external device is determined based on a state of the information processing apparatus. Power is supplied to the external device, based on a request from the external device as to the power supply capability to be presented to the external device. In a case where the state of the information processing apparatus has changed, the power supply capability to be presented to the external device is changed based on the changed state.

Information processing apparatus capable of supplying power to external device, printing apparatus, method of controlling information processing apparatus, method of controlling printing apparatus, and storage medium

An image processing apparatus includes a first image processing unit having a fixed image processing function to perform image processing of image data. A second image processing unit has a fixed image processing function to perform image processing of image area data. A reconfigurable image processing unit is capable of having selectively, by reconfiguration of an architecture of the reconfigurable image processing unit, one of least a first image processing function for image processing of image data and a second image processing function for image processing of image area data. A control unite reconfigures the architecture of the reconfigurable image processing unit to have one of at least the first image processing function and a second image processing function on a basis of whether the image processing apparatus processes a color image or a monochrome image.

Image processing apparatus and method

A clock supply apparatus for supplying clock signals to a plurality of circuit blocks includes a supply unit configured to supply, to reset the plurality of circuit blocks, a clock signal rising at timing different from one circuit block to another to each of the plurality of circuit blocks.

Clock supply apparatus

An image compression apparatus performs image compression on high-resolution image data of various resolutions while reducing the circuit size. A generation unit generates complementary information based on an arrangement pattern of pixel values in each of the divided blocks each including 2 by 2 pixels. Further, image data of 1/(2^M) times the resolution is compressed using a first compression method, and image data of 1/(2^N) times the resolution is compressed using a second compression method. The apparatus determines whether to cause a combination of the complementary information and first compressed data to be output, or a combination of the complementary information and second compressed data to be output, based on the data size of each.

Image compression apparatus and image compression method

This invention converts Packbit-encoded data into new Packbit-encoded data which allows to have a throughput=M. a extraction unit separates inputted encoded data into length information and data information, and outputs them to a conversion unit. The conversion unit has a count unit which cumulatively counts the number of output data after decoding indicated by the separated length information. The conversion unit divides length information of interest into first length information and second length information as needed, outputs the first length information, and sets the second length information as an initial count target to be counted by the count unit, so that the counted number N of output data reaches the throughput=M. The conversion unit combines the generated length information and the separated data information, and outputs new Packbit-encoded data.

Data conversion apparatus and control method thereof

An image processing apparatus provides numerical signal generator for sequentially generating and outputting regular binary numerical signals synchronous with clock signal, bit exchanger for generating and outputting, from the output signal of the numerical signal generator being managed as input signal, signal that order of bits in the input signal has been exchanged or signal that the bits in the input signal have been reversed, controller for controlling the bit order exchange operation or the bit reversal operation of the bit exchanger, and storage for storing image data, and in the apparatus the image data divided into pixel data and one-dimensionally arranged and stored in the storage is read and output synchronous with the sequential operation of the numerical signal generator, and the output signal from the bit exchanger is read and output as address signal to perform rotation/reversal process to former image.

Growing community of inventors

Kawasaki, Japan

Naotsugu Itoh