Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Naoto Oshiyama

Kenta Yasufuku

Ikuo Magaki

Tokumasa Hara

Kenichiro Yoshii

Ryo Yamaki

Naoaki Kokubun

Kosuke Hatsuda

Kohei Oikawa

Naomi Takeda

Toshio Fujisawa

Akira Yamaga

Daisuke Iwai

Satoshi Kaburaki

Shirou Fujita

Yu Nakanishi

Arata Miyamoto

Takashi Ogasawara

Hiroyasu Nakatsuka

Masanori Yamato

Shigenori Sugimoto

Seiichiro Sakurai

According to one embodiment, a non-volatile first memory includes a plurality of first storage areas. A second memory stores a plurality of first addresses each is address information of a second storage area. The second storage area is a first storage area in a first state. A third memory stores a counted value for the second storage area. A determiner circuit reads, at a time of a read access to the first memory, at least one of the first addresses and compares the read second address with a third address to determine whether a third storage area is in the first state. The third address indicates a location of the third storage area. The third storage area is a first storage area to be read. An update circuit increments, for the third storage area, the counted value, when the third storage area is in the first state.

Memory system

According to one embodiment, a memory system, comprises a non-volatile memory; a first memory and a second memory; and a memory controller configured to receive a first logical address from a host in a first reading, read a first address conversion table corresponding to the first logical address from the non-volatile memory, and store, in the non-volatile memory, a second address conversion table of a first state stored in the first memory in a case where the first logical address corresponds to a second logical address stored in the second memory.

According to one embodiment, an information processing apparatus includes a host and a memory system. The host includes a main memory. The memory system includes a memory access unit and an interface unit. The memory access unit converts a first request into transmission information. The first request is a request for data transfer toward a memory region as a part of the main memory. The interface unit transmits transmission information according to an instruction from the memory access unit.

Information processing apparatus and memory system

According to one embodiment, a memory controller includes a first volatile memory, a second volatile memory, and a controller. The first volatile memory temporarily stores therein data acquired from outside. The controller controls the temporarily stored data to be transferred from the first volatile memory to a non-volatile memory, stores correspondence information of the transferred data to the non-volatile memory in the second volatile memory, and updates correspondence information stored in the non-volatile memory based on the correspondence information stored in the second volatile memory by using the first volatile memory after the data transfer as a work area. The correspondence information represents association between a logical address and a physical address of the data.

Memory controller, memory system and memory control method

According to one embodiment, a decoder of a memory controller includes: a syndrome calculating unit configured to calculate a syndrome based upon a code word read from the memory; an error locator polynomial generating unit configured to generate an error locator polynomial based upon the syndrome, and to obtain a number of errors based upon the generated error locator polynomial; and an error location calculating unit configured to calculate an error location based upon the error locator polynomial, wherein the process of the error location calculating unit is not executed, when the number of errors is not less than the maximum number of bits that can be corrected by the error locator polynomial generating unit.

Memory controller and semiconductor storage device

A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host.

A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.

Storage device

Growing community of inventors

Tokyo, Japan

Naoto Oshiyama